Abstract: A pad silicon oxide layer is deposited over the surface of a silicon substrate. A silicon nitride layer is deposited overlying the pad silicon oxide layer. Portions of the silicon nitride and pad silicon oxide layers not covered by a mask pattern are etched through and into the silicon substrate so as to provide a plurality of wide and narrow trenches within the silicon substrate that will form the device isolation regions. Channel-stops are selectively ion implanted through the openings into the substrate underneath the trenches. The silicon nitride and pad oxide layers are removed. A thin silicon oxide layer is grown conformally on all surfaces of the substrate and within the trenches. A thick layer of silicon oxide is deposited over the surface of the substrate completely filling the trenches wherein the thick silicon oxide layer is planarized over the narrow trenches but is not planarized over the wide trenches.

Abstract: A new method of fabricating a convex charge coupled device is achieved. A silicon oxide layer is formed over the surface of a silicon substrate and patterned with a charge coupled device (CCD) electrode mask to provide openings to the silicon substrate. Nitride spacers are formed on the sidewalls of the openings. The integrated circuit is coated with a spin-on-glass layer. After curing, the spin-on-glass layer is etched back to expose the nitride spacers. Removing the nitride spacers leaves a second set of openings to the silicon substrate. Ions are implanted into the substrate through the second set of openings. The oxide layer is removed. The wafer is globally oxidized resulting in a thermal oxide layer with undulatory thickness. The thermal oxide is removed leaving a convex surface on the silicon substrate. A gate oxide layer is formed on the convex surface of the silicon substrate.

Abstract: A new method of local oxidation using a salicide recessed oxidation process is described. A thin silicon oxide layer is formed over the surface of a silicon substrate. A layer of silicon nitride is deposited overlying the silicon oxide layer. The silicon oxide and silicon nitride layers are patterned to provide openings exposing portions of the silicon substrate that will be oxidized subsequently. A metal layer is deposited overlying the silicon nitride layer and within the openings to the substrate. Channel-stops are ion implanted into the substrate through the openings. The salicide is formed by reacting the metal layer with the silicon substrate where the metal layer contacts the substrate within the openings. The metal silicide regions are removed, leaving recesses in the silicon surface within the openings. Field oxide regions are grown within the openings. Finally, the silicon nitride and silicon oxide layers are removed thereby completing local oxidation of the integrated circuit.

Abstract: A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process of this invention has been simplified by not using several of the high thermal cycle process steps believed to be necessary for successfully making a polycide gate lightly doped drain MOS FET integrated circuit. These steps are (1) the thermal oxidation after the polycide etching step, (2) the densification step after the blanket deposition of silicon dioxide layer for the spacer preparation, and (3) the silicon oxide capping of the refractory metal silicide layer after the spacer formation by anisotropically etching. The result is a process that provides a non-peeling polycide gate lightly doped drain MOS FET integrated circuit device.

Abstract: A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process of this invention has been simplified by not using several of the high thermal cycle process steps believed to be necessary for successfully making a polycide gate lightly doped drain MOS FET integrated circuit. These steps are (1) the thermal oxidation after the polycide etching step, (2) the densification step after the blanket deposition of silicon dioxide layer for the spacer preparation, and (3) the silicon oxide capping of the refractory metal silicide layer after the spacer formation by anisotropically etching. The result is a process that provides a non-peeling polycide gate lightly doped drain MOS FET integrated circuit device.