Abstract: In accordance with the invention a rough overlayer, e.g., a tungsten film, is used to define a plurality of pillars in a polysilicon electrode layer. This increases the surface area of the polysilicon electrode and thus increases capacitance of a capacitor incorporating the electrode layer in a DRAM cell.

Abstract: A source/drain structural configuration suitable for metal-oxide semiconductor field-effect transistors is provided, having a wedge-shaped configuration with a thickness that increases in the direction from its end near to one the channel of the transistor toward the other end. The source/drain configuration includes a shallow junction advantageously formed to reduce sheet resistance and prevent the hot carrier punchthrough effect. The wedge-shaped source/drain configuration is fabricated by depositing a dielectric layer, which is flowable under thermal treatment, after the formation of a polysilicon gate electrode. After annealing, the dielectric layer is etched to form a wedge-shaped mask. The resulting mask has a thickness that decreases in the direction from its one end near the gate electrode toward the other end. The presence of the wedge-shaped shielding masks facilitates the formation of a pair of wedge-shaped source/drain regions on the substrate via implementation of an ion implantation procedure.

Abstract: A method of forming a metal via on a semiconductor substrate having a metal layer and a dielectric layer on the metal layer, which uses an intermediate mask layer as a mask in forming the metal via instead of using a photoresist as a mask. Therefore, the spin-on glass (SOG) layer in the dielectric layer is not exposed to plasma or solvent, thereby preventing the formation of polymers which cause poor step coverage and sometimes even contact failure in the metal via.

Abstract: This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.

Abstract: A method of fabricating a stress-free isolation layer for semiconductor integrated circuit that solves the problems of crystalline defects and the degraded characteristics of devices due to the presence of structural stresses. Partial trench etching is employed to form at least one narrow trenches, followed by anneal-treating to release stress and eliminate crystalline defects therein. Isolating material is then filled into the narrow trenches to form a complete stress-free isolation layer.

Abstract: A new method of forming stress releasing voids within the intermetal dielectric of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. A silicon oxide layer is deposited overlying the first patterned metal layer. A silicon nitride layer is deposited over the silicon oxide layer. A metal layer is deposited over the silicon nitride layer and etched to form silicon nodules on the surface of the silicon nitride layer. The silicon nitride layer is etched away to the underlying silicon oxide layer wherein the silicon nitride under the silicon nodules remains in the form of pillars. The surface of the silicon oxide layer is coated with a spin-on-glass material which is baked and cured. The silicon nodules and silicon nitride pillars are removed, leaving voids within the spin-on-glass layer.

Abstract: A method of forming a self-aligned trenched contact in the fabrication of an integrated circuit is described. Semiconductor device regions are formed in and on a semiconductor substrate wherein the semiconductor device regions include gate electrodes on the surface of the semiconductor substrate and source/drain regions within the semiconductor substrate. Spacers are formed on the sidewalls of the gate electrodes. A layer of silicon oxide is deposited over the surface of the substrate wherein the silicon oxide contacts the source/drain regions within the substrate between the gate electrodes. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned trenched contact between the gate electrodes. The silicon oxide is etched away to provide an opening to the silicon substrate using the patterned photoresist and the sidewall spacers as a mask.

Abstract: In the fabrication of VLSI circuits, the diffusion barrier layer on the pad areas are removed prior to the formation of metal layer. Metal layer on the pad areas are thus directly contact with the underlying SiO.sub.2 layer, thereby improving the pad bonding yield.

Abstract: A method is described for fabricating an integrated circuit in which the gate electrodes and gate dielectric silicon oxide are protected from electrical charge damage during ion implantation. A thin conducting layer is deposited over the pattern of gate electrodes/gate dielectric silicon oxide wherein the conducting layer is grounded to the silicon substrate. The high-dose ion implantation is applied through the conducting layer which layer grounds the electrical charge resulting from the ion implantation, and hence protects the gate electrodes from charge damage. The electron "flood gun" need not be used.

Abstract: The invention describes a non-trenched buried contact for local interconnections in VLSI devices and provides a method for forming the non-trenched buried contact. By using trenched isolation and a trench polysilicon gate structure the buried contact process can be implemented so that there are no unwanted trenches formed in the area of the buried contact. The invention permits excellent planarization of the device prior to pre-metal dielectric and metal deposition.

Abstract: A new method of local oxidation using a multiple process is described. A thin silicon oxide layer is formed over the surface of a silicon substrate. A layer of silicon nitride is deposited overlying the silicon oxide layer. The silicon oxide and silicon nitride layers are patterned to provide openings of the smallest size exposing portions of the silicon substrate to he oxidized and growing field oxide regions within these smallest size openings. The patterning and growing of field oxide regions is repeated for each larger size of opening required. The silicon nitride and silicon oxide layers are removed, thereby completing local oxidation of the integrated circuit.

Abstract: A new method of local oxidation by means of forming a plurality of silicon trenches is described. Portions of the insulating layer over the surface of a silicon substrate not covered by a mask pattern are etched through exposing the portion of the silicon substrate that will form the device isolation region. A first trench is etched into the exposed portion of the substrate. A layer of silicon nitride is deposited over the insulating layer and within the trench. A layer of an aluminum-silicon alloy is deposited overlying the silicon nitride layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the silicon nitride layer. The nodules are oxidized to form silicon dioxide nodules. Using the silicon dioxide nodules as a mask, the silicon nitride layer is etched through to the insulating layer where it exists and to the silicon substrate surface where it is exposed and a set of narrow trenches is etched into the exposed portions of the substrate.

Abstract: A method of local oxidation using trench-around technology is described. A first silicon oxide layer is deposited over the surface of a silicon substrate. A plurality of wide and narrow openings are etched through portions of the first silicon oxide layer not covered by a mask pattern to the silicon substrate. A layer of silicon nitride is patterned to form a set of spacers on the sidewalls of the patterned first silicon oxide layer which will fill the narrow openings. The first silicon oxide layer is partially etched away whereby the substrate within the central portions of the wide openings will be etched to form shallow trenches. The patterned first silicon oxide layer and the silicon nitride spacers are covered with spin-on-glass material which is baked and cured, then etched back leaving the spin-on-glass material only within the wide openings within the shallow trenches.

Abstract: A new method of local oxidation by means of stress-releasing narrow trenches is described. Pad silicon oxide, silicon nitride, and silicon dioxide layers are formed on a silicon substrate. Portions of these layers not covered by a mask are etched away to provide an opening to the silicon substrate where the field oxidation region is to be formed. The silicon substrate is etched into where it is exposed to form a shallow trench within the opening. Silicon dioxide spacers and silicon nitride spacers are formed on the sidewalls of the opening. The silicon substrate is coated with a spin-on-glass layer. The spin-on-glass layer is cured, then etched back so that the spin-on-glass layer remains only within the shallow trench not covered by the spacers. The silicon nitride spacers are stripped away. Narrow trenches are etched into the silicon substrate under the silicon nitride spacers. The silicon dioxide spacers and spin-on-glass layer are removed leaving the opening entirely exposed.

Abstract: A method of fabricating an integrated circuit which maintains global planarization throughout the process flow is achieved. Trenched isolation regions are formed within a silicon substrate. Trenched polysilicon gate electrodes are formed within the silicon substrate and within the trenched isolation regions. Source and drain regions are formed within the silicon substrate wherein the top surfaces of the trenched isolation regions, the trenched polysilicon gate electrodes, and source and drain regions form a planarized top surface of the silicon substrate. A pre-metal dielectric layer is deposited over the planarized top surface. Contact openings are formed by etching through the dielectric to the trenched polysilicon gate electrodes and to the source and drain regions. The contact openings are filled with tungsten plugs wherein the top surfaces of the pre-metal dielectric and the tungsten plugs form a planarized top surface of the silicon substrate.

Abstract: A first thin silicon oxide layer is formed the surface of a silicon substrate. A silicon nitride layer is deposited overlying said first thin silicon oxide layer. Portions of the silicon nitride layer and the first thin silicon oxide layer not covered by a mask pattern are etched through to the silicon substrate to provide a plurality of wide and narrow openings exposing portions of the silicon substrate that will form the device isolation regions. A layer of aluminum is deposited overlying the patterned nitride and first thin silicon oxide layers. A first layer of silicon oxide is deposited overlying the aluminum layer. The substrate is annealed whereby the aluminum layer reacts with the exposed portions of the silicon substrate within the openings to form an aluminum-silicon alloy wherein the alloy forms trenches into the surface of said substrate.

Abstract: A method of metallization using a tungsten plug is described. A contact hole is opened to the semiconductor substrate through an insulating layer covering semiconductor structures in and on the semiconductor substrate. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A tungsten plug is formed within the contact opening. The glue layer is removed except for portions of the glue layer underneath the tungsten plug and on the lower sides of the tungsten plug. Ditches are left on the upper sides of the tungsten plug where the glue layer has been removed. The ditches around the tungsten plug are filled with a dielectric material. A second metallization is deposited and patterned. The patterned second metallization does not extend over one side portion of the tungsten plug; that is, there is no dog-bone formation.

Abstract: A new method of fabricating a polycide gate structure is described. A gate polysilicon layer is provided overlying a gate oxide layer on the surface of a semiconductor substrate. A thin conducting diffusion barrier layer is deposited overlying the gate polysilicon layer. A layer of tungsten silicide is deposited overlying the thin conducting diffusion barrier layer wherein a reaction gas used in the deposition contains fluorine atoms and wherein the fluorine atoms are incorporated into the tungsten silicide layer. The gate polysilicon, thin conducting diffusion barrier, and tungsten silicide layers are patterned to form the polycide gate structures.

Abstract: A new metallization method for metal lines formation of a very large scale integrated circuit (VLSI) is described. The metal lines are formed in a "wavy" or "snaky" pattern. It is a "wavy" pattern when the metal line goes through a vertically vibratory path. It is a "snaky" pattern when a metal line goes through a horizontally vibratory path. This includes both uniform and random "wavy" and "snaky" patterns. A metal line can also be formed in a pattern that is both "wavy" and "snaky." For the "wavy" pattern, the topography under the metal lines is fabricated using, for example, field oxide. The "wavelength" can vary from 1 to 10 micrometers. A slight modification of the metal mask can produce the "snaky" structure of the metal line. The stresses will be released by a small curvature change of the metal line. For the contact structures, a multi-contact layout with "wavy" structure can release more stress than can a single-contact layout of the same contact area.

Abstract: A first insulating layer is deposited over the surface of a silicon substrate. Those portions of the first insulating layers not covered by a mask pattern are etched through to the silicon substrate so as to provide a plurality of wide and narrow openings exposing portions of the silicon substrate that will form the device isolation regions. A second insulating layer is deposited overlying the patterned first insulating layer. A layer of an aluminum-silicon alloy is deposited overlying the second insulating layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the second insulating layer. The second insulating layer is etched through to the first insulating layer where it exists and to the silicon substrate surface where the substrate is exposed within the wide and narrow openings. A first set of narrow trenches is etched into the exposed portions of the silicon substrate within the wide and narrow openings using the silicon nodules as a mask.