Abstract: A technique for making a MOST capacitor for use in a DRAM cell utilizes silicon nodules after metal etching. The silicon nodules are used as a mask to selectively form deep grooves in a polysilicon electrode of the capacitor.

Abstract: A MOST capacitor for use in a DRAM cell is formed by depositing a conductive polysilicon electrode layer on the substrate. Oxide lines are then formed on the polysilicon layer. Using the oxide lines as a mask, pillars are etched in the polysilicon electrode layer.

Abstract: A MOST capacitor for use in a DRAM cell by using non-uniform silicide formations on polysilicon to define a plurality of polysilicon pillars. Unreacted polysilicon islands are used as a mask to selectively form the pillars in the polysilicon electrode layer.

Abstract: The invention describes a non-trenched buried contact for local interconnections in VLSI devices and provides a method for forming the non-trenched buried contact. By using trenched isolation and a trench polysilicon gate structure the buried contact process can be implemented so that there are no unwanted trenches formed in the area of the buried contact. The invention permits excellent planarization of the device prior to pre-metal dielectric and metal deposition.

Abstract: A new isolation technology fabrication process is provided including the step of forming a trench in a semiconductor material. Then, several poly walls are formed in the trench. The poly walls are oxidized to form a single oxide isolation region filling the trench.

Abstract: A method of forming an isolated structure on a silicon substrate having a silicon-on-insulator (SOI) structure using liquid phase deposition which is capable of selectively depositing oxide only in trenches of the substrate. Recessed field oxides are grown with the same height and leave a flat surface on a top surface of the substrate. The liquid phase deposition is performed using saturated hydrofluosilicic acid as a reactant.

Abstract: An silicon-on-insulator (SOI) isolation structure of a silicon substrate, which has a buried gap between active regions and the substrate, and supporting pillars formed of an insulating material to support the active regions. The buried gap is formed by etching an implanted buried silicon nitride layer. Since the dielectric constant of the buried gap is about 1, the dielectric effect and isolating effect of this structure are greatly improved.

Abstract: A method of forming field oxides with curvilinear boundaries between active regions on a substrate in an integrated circuit (IC) so that the stresses induced in the active regions due to the formation of field oxide can be reduced. Problems like junction leakage are reduced due to the rounded boundaries of the field oxides.

Abstract: A MOST capacitor for use in a DRAM is formed by using BPSG precipitates after densification as a mask for etching a BPSG layer to form BPSG islands. The BPSG islands are then used as a mask for etching a polysilicon layer to form pillars in the polysilicon layer.

Abstract: A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.

Abstract: A new planarized device isolation structure within a semiconductor substrate is described. The device isolation structure comprises narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide, wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein the shallow trench is filled with a field oxide. The top surface of the narrow and wide device isolation regions and the semiconductor substrate is planarized.

Abstract: This invention describes a diving channel device structure and a method of forming the diving channel device structure using deep vertical trenches formed in a silicon substrate crossing shallow vertical trenches formed in the same silicon substrate. The deep vertical trenches are filled with a first heavily doped polysilicon to form the sources and drains of field effect transistors. The shallow vertical trenches are filled with a second highly doped polysilicon to form the gates of the transistors. The device structure provides reduced drain and source resistance which remains nearly constant when the device is scaled to smaller dimensions. The device structure also provides reduced leakage currents and a plane topography. The device structure forms a large effective channel width when the device is scaled to smaller dimensions.

Abstract: A MOS capacitor structure in accordance with the invention is formed by depositing a polysilicon electrode layer on the substrate. Oxide regions are then formed on the polysilicon layer. Using the oxide regions as a mask, pillars are etched in the polysilicon electrode layer.

Abstract: A method for fabricating a stacked storage capacitor on a dynamic random access memory (DRAM) cell with increased capacitance was accomplished. The stacked capacitor is used with a field effect transistor (FET) as part of a dynamic random access memory (DRAM) cell for storing data in the form of stored charge on the capacitor. The method for making the capacitor involves forming a bottom electrode from a single polysilicon layer having a fin-shaped structure, and then using a second polysilicon layer and a plasma etch back to create a second self-aligned fin-like structure that significantly increases the surface area of the capacitor bottom electrode. The capacitor structure is then completed by forming a thin capacitor dielectric layer on the bottom electrode and depositing a third polysilicon layer to form the top electrode and complete the capacitor with significantly increased capacitance and an economy of processing steps.

Abstract: A method of forming an isolation structure on a silicon substrate using liquid phase deposition which is capable of selectively depositing oxide only in trenches of the substrate, to grow recessed field oxides of same height, and leave a flat surface of the substrate. The liquid phase deposition is performed using saturated hydrofluosilicic acid as a reactant.

Abstract: A new method of fabricating an integrated circuit which maintains global planarization throughout the process flow is achieved. Trenched isolation regions are formed within a silicon substrate. Trenched polysilicon gate electrodes are formed within the silicon substrate and within the trenched isolation regions. Source and drain regions are formed within the silicon substrate wherein the top surfaces of the trenched isolation regions, the trenched polysilicon gate electrodes, and source and drain regions form a planarized top surface of the silicon substrate. A pre-metal dielectric layer is deposited over the planarized top surface. Contact openings are formed by etching through the dielectric to the trenched polysilicon gate electrodes and to the source and drain regions. The contact openings are filled with tungsten plugs wherein the top surfaces of the pre-metal dielectric and the tungsten plugs form a planarized top surface of the silicon substrate.

Abstract: A capacitor structure suitable for use in Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) devices and its method of fabrication is disclosed. The capacitor includes a main or root trench extending vertically into the silicon substrate and at least one buried trench extending horizontally into the side wall of the main trench. The enlarged trench sidewall surface area as a result of the added buried trenches increases the total capacitance of the capacitor and it suitable for use with high density, high data volume memory devices. The buried trenches are formed by implanting oxygen or nitrogen ions into the designated depths of the silicon substrate, subsequently annealing the entire substrate at the absence of gaseous oxygen, and etching away the converted silicon dioxide or silicon nitride. The formed trench system can reduce the accumulation of the structural stress to avoid the formation of crystalline defects and obtain the resulting device with better quality.

Abstract: A new method of forming device isolation regions on a silicon substrate is provided. This method comprises the following steps: a pad oxide layer is formed on the silicon substrate; a silicon nitride layer is formed on the pad oxide layer; portions of the silicon nitride and pad oxide layers not covered by a mask pattern are etched through and into the silicon substrate so as to provide a plurality of wide and narrow trenches within the silicon substrate that will form the device isolation regions; silicon nitride spacers are formed on the sidewalls of the trenches; a first field oxide layer is grown on bottoms of the trenches by using thermal oxidation wherein a thin oxide layer is also formed on the silicon nitride layer; the thin oxide layer, silicon nitride layer, silicon nitride spacers and pad oxide layer are removed, respectively; and a second field oxide layer is formed on the first field oxide layer by using liquid phase deposition so as to fill all of the trenches.

Abstract: A silicon-on-insulator (SOI) isolation structure of a silicon substrate, which has buried gaps between active regions and the substrate, and field oxides to support the active regions. The buried gap is formed by etching an implanted buried silicon nitride layer. Since the dielectric constant of the buried gap is approximately 1, the dielectric effect and isolating effect of this structure are greatly improved.

Abstract: A new method of metal deposition in an integrated circuit is described. Semiconductor device structures are provided in and on a semiconductor substrate. At least one patterned conductive layer is provided for contacting the active elements of the device structures. The surface of the patterned conductive layer structure is irregular with horizontal and vertical components. An insulating layer is provided over the irregular structure patterned conductive layer. The insulator layer is covered with at least one spin-on-glass layer to fill the valleys of the irregular structure. The spin-on-glass layer is baked and cured, then covered with a second insulator layer. The spin-on-glass and two insulator layers are etched to provide openings to the patterned conductive layer wherein the etching is performed at low temperature so as to decrease the possibility of device degradation. The exposed spin-on-glass layer within the openings is degassed at a high temperature.