Patents by Inventor Wei-An HSIEH

Wei-An HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6606623
    Abstract: An apparatus and method of content-based image retrieval generate a plurality of training images, including a first part and a second part. Each training image of the first part is labeled as one of a positive bag or a negative bag. The training image is labeled a positive bag if the training image has a desirable character and labeled a negative bag if the training image does not have a desirable character. A set of N1 training images is identified from a set of all training images of the second part, which identified images have a feature most closely matching a first feature instance of a training image labeled as a positive bag. A first value corresponding to the first feature instance is calculated, based on the number of images labeled as positive bags that are identified in the set of N1 training images.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: August 12, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Jun-Wei Hsieh, Cheng-Chin Chiang, Yea-Shuan Huang
  • Publication number: 20030044067
    Abstract: In order to improve pattern recognition, various kinds of transformations are performed on an input object. One or more recognition algorithms are then performed on the input object transforms in addition to the input object itself. By performing recognition algorithms on an input object and its transforms, a more comprehensive set of recognition results are generated. A final recognition decision is based upon an input object and its transforms by aggregating the recognition results.
    Type: Application
    Filed: August 24, 2001
    Publication date: March 6, 2003
    Inventors: Yea-Shuan Huang, Chun-Wei Hsieh
  • Patent number: 6518137
    Abstract: Steep spacer is formed by using depositing and etching of dual conformal layers. A first conformal dielectric layer is deposited on a substrate with a gate electrode structure formed thereon. Then, a second conformal layer is deposited on the first conformal dielectric layer. The second conformal layer is anisotropically etched to form a first spacer on the sidewall of the first conformal dielectric layer. Next, the first conformal layer is anisotropically etched by using the first spacer as a mask to form a second spacer on the sidewall of the gate electrode structure. Then, the first spacer is removed and the second spacer is steep.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: February 11, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Shou-Wei Hsieh, Chiu-Tsung Huang
  • Publication number: 20030007685
    Abstract: The present invention relates to methods and systems for an illuminant compensation. In particular, these methods and systems include a method for operations on an image, for example, an image of a human face. In the described methods and systems, it is determined for each pixel in the image whether it is part of the face region. A surface fitting is then determined based on only the pixels that are determined to be part of the face region. Also, described are methods and systems for image normalization wherein the standard deviation and average for the gray levels of the pixels are determined and then used to normalize the image so that the gray level for each of the pixels falls between a particular range.
    Type: Application
    Filed: April 26, 2001
    Publication date: January 9, 2003
    Inventors: Yao-Hong Tsai, Yea-Shuan Huang, Cheng-Chin Chiang, Chun-Wei Hsieh
  • Publication number: 20020176609
    Abstract: A system and a method for rapidly tacking multiple faces are disclosed. A face-like region generator finds a face-like region by skin color, motion, and silhouette information. A face tracking engine tracks faces based on new and old faces, and skin colors provided by the face-like regions. The tracked face is fed into a face status checker for determining whether the face-like regions are old faces tracked in a previous frame or are possible new faces. If the face-like regions are old faces, a face verification engine checks whether there exists a predefined percentage of overlapping area between an old face and a skin region. If yes, the old face is still in the current frame and its position is in the center of the skin region, otherwise, the position of the old face is found by a correlation operation.
    Type: Application
    Filed: August 17, 2001
    Publication date: November 28, 2002
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-Wei Hsieh, Yea-Shuan Huang
  • Patent number: 6477268
    Abstract: A method is described for producing smooth transitions between a source vista and a destination vista with unknown camera axes in panoramic image based virtual environments. The epipoles on the source vista and the destination vista are determined to align the vistas. Corresponding control lines are selected in the vistas to compute the image flow between the vistas and to densely match the pixels. In-between image frames are computed by forward-resampling the source vista and backward-resampling the destination vista.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: November 5, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Chin Chiang, Jun-Wei Hsieh, Tse Cheng
  • Publication number: 20020128791
    Abstract: An Integrated Circuit (IC) of an electronic thermometer includes resistors and capacitors combination, logic switch system or formulated compensation parameter table being established therein for calibration of preset objective value of software and hardware utilized by the system to select optimum compensated resistors and capacitors arranged combination or the optimum parameter group within the compensation parameter table, the selected combination being written into the internal established or externally mounted EEPROM or Memory such that the internally established programs in the IC accesses the resistors and capacitors combination or the compensated parameters.
    Type: Application
    Filed: March 8, 2001
    Publication date: September 12, 2002
    Inventors: Min-Yung Chen, Chih-Wei Hsieh
  • Publication number: 20020098659
    Abstract: Steep spacer is formed by using depositing and etching of dual conformal layers. A first conformal dielectric layer is deposited on a substrate with a gate electrode structure formed thereon. Then, a second conformal layer is deposited on the first conformal dielectric layer. The second conformal layer is anisotropically etched to form a first spacer on the sidewall of the first conformal dielectric layer. Next, the first conformal layer is anisotropically etched by using the first spacer as a mask to form a second spacer on the sidewall of the gate electrode structure. Then, the first spacer is removed and the second spacer is steep.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 25, 2002
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wei Hsieh, Chiu-Tsung Huang
  • Patent number: 6207501
    Abstract: A method of fabricating a flash memory is disclosed: firstly, a P-type silicon substrate is divided into a PMOS area, an NMOS area, and a flash memory area. The first polysilicon layer and the first oxide layer are formed at the flash memory area. Thereafter, the second polysilicon layer, the second oxide layer, and a layer of TEOS are formed. The first photo resist is then formed to define the gate pattern of the flash cell array, and then a process of N+ ion implantation is performed to form the source and drain of the flash cell array. After stripping the first photo resist, the second photo resist is formed to define the gate pattern at the NMOS area, and a process of N+ ion implantation is performed to form the NLDD structure. After stripping the second photo resist, the first sidewall is formed, and then a process of N− ion implantation is performed to form the NMOS source/drain. The third photo resist is then formed to define the gate pattern at the PMOS area.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: March 27, 2001
    Assignee: United Microelectronics. Corp.
    Inventors: Shou-Wei Hsieh, Shiou-Han Liaw
  • Patent number: 6028584
    Abstract: A method and apparatus for displaying a selected portion of a panoramic image onto a view plane is provided. The method provides an environment map in the form of a plurality of pixel values representative of the panoramic image. A first portion of the pixel values representative of a selected first area of the panoramic image is mapped to a projection buffer. A second portion of the first portion of pixel values, representative of a desired area of the panoramic image to be viewed is mapped to the view plane. The view plane is displayed on the display.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: February 22, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Chin Chiang, Chun-Wei Hsieh, Tse Cheng
  • Patent number: 6010925
    Abstract: A method of making dual-gate structure with only three masking steps is provided.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: January 4, 2000
    Assignee: Utek Semiconductor, Corp.
    Inventor: Shou-Wei Hsieh
  • Patent number: 6011558
    Abstract: A pair of images are stitched together by warping the pair of images into an environment map representative of a panoramic image. A first edge and a corresponding second edge for each of the first and second images, respectively, are detected. A set of edge position coordinates along the edge of the first warped image is determined. A set of possible matched solutions from the edge position coordinates of the first and second edge are generated. An optimum matched offset from the set of possible matched solutions is determined. Because the set of possible matched solutions is small and compact, the optimum matched offset can be determined efficiently from the set of solutions.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: January 4, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Wei Hsieh, Tse Cheng, Cheng-Chin Chiang, Shu-Cheng Huang
  • Patent number: 5929755
    Abstract: A pressure gauge for a pneumatic tire includes a casing, a pressure responsive signal-generating device disposed in the casing, an electric power source connected electrically to the signal-generating device, and a switch assembly connected electrically to the electric power source. The switch assembly includes a normally open reed switch, a magnet member and a magnet support. The reed switch is electrically connected to the electric power source. The magnet member is disposed movably in the casing to produce a magnetic field for activating the reed switch to an ON position, and is movable toward the reed switch via a centrifugal force produced upon rotation of the pneumatic tire. The magnet support is disposed adjacent to the reed switch to movably hold the magnet member, and has a biasing unit to provide a biasing action to move the magnet member away from the reed switch when the centrifugal force is absent.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: July 27, 1999
    Assignee: Tien-Tsai Huang
    Inventor: Chin-Wei Hsieh
  • Patent number: 5801997
    Abstract: A reciprocating or ping-pong voltage boosting circuit is described. The ping-pong boosting circuit has a first and a second boost circuit connected between the power supply voltage source and a ground reference point to generate a first instance and a second instance of a boost voltage. The reciprocating circuit has a switching circuit to alternately place the first and second instance of the boost voltage upon the signal line to bring the voltage level of the signal line to that of the boost voltage. A boost control circuit will provide a switching signal that will control the alternate placing of the first and second instances of the boost voltage upon the signal line. The boost control circuit will provide a boost signal that will cause the first and second boost circuits to generate the first and second instances of the boost voltage.
    Type: Grant
    Filed: June 24, 1997
    Date of Patent: September 1, 1998
    Assignee: Etron Technology, Inc.
    Inventors: Chung-Wei Hsieh, Yung-Ching Hsieh, Tah-Kang Joseph Ting