Patents by Inventor WEI-AN LAI

WEI-AN LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240205448
    Abstract: Video processing methods for coding a current block comprise receiving input data of a current block, checking whether a sub-block motion compensation coding tool is applied to the current block based on a size, width, or height of the current block, a size, area, shape, width, or height of sub-blocks partitioned from the current block, an inter prediction direction of a sub-block Motion Vector (MV), primary MV, or one of control point MVs of the current block, a primary MV, the control point MVs, affine parameters; encoding or decoding the current block using the sub-block motion compensation coding tool or another coding tool according to a result of the checking indicating whether application of the sub-block motion compensation coding tool is valid or invalid; and a MV clipping process is applied to each sub-block in the current block if the checking result is false, indicating the validity is invalid.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 20, 2024
    Inventors: Tzu-Der CHUANG, Ching-Yeh CHEN, Chen-Yen LAI, Chih-Wei HSU
  • Publication number: 20240203370
    Abstract: A display module and a driving method thereof, and a display device are provided. The display module includes a backlight structure including a plurality of backlight partitions. The display module includes a first display mode and a second display mode. Resolution of the display module in the first display mode is greater than the resolution of the display module in the second display mode. In the first display mode, a quantity of the plurality of backlight partitions of the backlight structure is n1, and an area of one of the plurality of backlight partitions of the backlight structure is S1. In the second display mode, the quantity of the plurality of backlight partitions of the backlight structure is n2, and the area of one of the plurality of backlight partitions of the backlight structure is S2, with n1>n2, and S1<S2.
    Type: Application
    Filed: March 8, 2023
    Publication date: June 20, 2024
    Inventors: Jian LIU, Liu WANG, Zhijie WANG, Shumao WU, Wei WU, Guochang LAI
  • Patent number: 12011859
    Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.
    Type: Grant
    Filed: July 4, 2023
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Feng Weng, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Sheng-Hsiang Chiu, Yao-Tong Lai, Chia-Min Lin
  • Publication number: 20240194682
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Application
    Filed: January 22, 2024
    Publication date: June 13, 2024
    Applicant: Tiawan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien WU, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Publication number: 20240189292
    Abstract: The present invention relates to a series of substituted pyridine-2,4-dione derivatives and preparation methods therefor, and in particular, to a compound represented by formula (I) and a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 13, 2024
    Inventors: Xiaobing YAN, Wei LAI, Charles Z. DING, Shuhui CHEN
  • Patent number: 12009281
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Po-Yuan Teng, Chi-Hui Lai
  • Patent number: 12009362
    Abstract: A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai, Shang-Wen Chang
  • Publication number: 20240183025
    Abstract: Embodiments of the present disclosure provide a substrate processing system. In one embodiment, the system includes a chamber, a target disposed within the chamber, a magnetron disposed proximate the target, a pedestal disposed within the chamber, and a first gas injector disposed at a sidewall of the chamber. The first gas injector includes a first gas channel extending through a body of the first gas injector, the first gas channel has a first gas outlet. The first gas injector also includes a second gas channel extending through the body of the first gas injector, wherein the second gas channel has a second gas outlet. The second gas channel includes a first portion, and a second portion branching off from an end of the first portion, wherein the second portion is disposed at an angle with respect to the first portion, and the first gas injector is operable to rotate about a longitudinal center axis of the body of the first gas injector.
    Type: Application
    Filed: January 5, 2024
    Publication date: June 6, 2024
    Inventors: Po-Wei WANG, Chao-Hsing LAI
  • Patent number: 12003837
    Abstract: A dual-lens camera system includes a first lens, a second lens, an image sensor corresponding to a position of the first lens, and a reflecting assembly. The reflecting assembly includes a first reflecting member and a second reflecting member corresponding to a position of the second lens. The first reflecting member is movable between a first position at which an optical path from the first lens to the image sensor is blocked but an optical path from the second reflecting member to the image sensor is not blocked, and a second position at which the optical path from the first lens to the image sensor is not blocked but the optical path from the second reflective member to the image sensor is blocked. Only one image sensor is used in the dual-lens camera system, which saves cost and takes up less internal space of the electronic device.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: June 4, 2024
    Assignee: TRIPLE WIN TECHNOLOGY (SHENZHEN) CO. LTD.
    Inventors: Wen-Ching Lai, Chao-Yu Qin, Zhi-Wei Li
  • Publication number: 20240173080
    Abstract: A navigation system of a surgical robot includes an endoscope and a navigation device. The endoscope is configured to capture an internal image of a tissue. The navigation device is configured for: analyzing the internal image to obtain a depth information of the tissue; determining whether there are several passages in the tissue according to the depth information; and selecting the passage that conforms to a path planning setting when the passages appear in the tissue.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 30, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Kai WANG, Tseng-Wei LAI
  • Publication number: 20240176143
    Abstract: A head-mounted display, controlling method, and non-transitory computer readable storage medium thereof are provided. The head-mounted display determines a first posture among a plurality of postures based on a plurality of real-time images. The head-mounted display generates a first gesture among a plurality of gestures corresponding to a user according to a plurality of inertial measurement parameters corresponding to a first body part of the user. The head-mounted display generates a control signal corresponding to a first output event among a plurality of output events based on the first gesture and the first gesture.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Chao-Hsiang Lai, Cheng-Han Hsieh, Tzu-Wei Huang
  • Publication number: 20240178214
    Abstract: An integrated circuit includes a horizontal routing track in a first metal layer, and a backside routing track in a backside metal layer. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. The horizontal routing track is conductively connected to a first terminal of a first transistor without passing through a routing track in another metal layer. The backside routing track is conductively connected to a second terminal of the first transistor without passing through a routing track in another metal layer. One of the first terminal and the second terminal is a gate terminal of the first transistor while another one the first terminal and the second terminal is either a source terminal or a drain terminal of the first transistor.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 30, 2024
    Inventors: Wei-An LAI, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20240178139
    Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.
    Type: Application
    Filed: February 8, 2024
    Publication date: May 30, 2024
    Inventors: Wei-An LAI, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20240170381
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240168266
    Abstract: An optical path folding element includes an optical portion, a connection portion, matte structures and a light blocking layer. The optical portion has an optical surface and two reflective surfaces. A light beam enters into the optical path folding element via the optical surface and is reflected inside the optical path folding element through the optical surface. Each reflective surface is configured to reflect the light beam again inside the optical path folding element. The connection portion has connection surfaces connected to the optical surface and the reflective surfaces. The matte structures are at least disposed on and integrally formed with the connection portion. Each unitary structure of the matte structures is tapered off and recessed from the connection portion, such that the outer surface of the connection portion has an undulating shape. The light blocking layer is at least disposed on the connection portion for blocking light.
    Type: Application
    Filed: October 3, 2023
    Publication date: May 23, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Chen Wei FAN, Syuan Ruei LAI, Jyun-Jia CHENG, Ming-Ta CHOU
  • Publication number: 20240170591
    Abstract: A method of fabricating a halide perovskite having a general formula of ABX3, wherein A, B, and X are inorganic elements and X is a halide, the method including a vapor-liquid-solid process triggered by a catalyst formed from a noble metal; A nanowire of the halide perovskite and a photoelectronic device thereof
    Type: Application
    Filed: November 21, 2022
    Publication date: May 23, 2024
    Inventors: Chung Yin Johnny Ho, You Meng, Zhengxun Lai, Wei Wang
  • Patent number: 11990510
    Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Ting Tsai, Chung-Wei Hung, Jung-Ting Chen, Ying-Hua Lai, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11990477
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 11989005
    Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: May 21, 2024
    Assignee: MediaTek Inc.
    Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
  • Publication number: 20240160828
    Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU