Patents by Inventor WEI-AN LAI
WEI-AN LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12043668Abstract: An antibody, or an antigen-binding fragment thereof, that binds specifically to human CSF-1R includes a heavy chain variable domain that contains a HCDR1 region having the sequence of SEQ ID NO: 4, a HCDR2 region having the sequence of SEQ ID NO: 5, and a HCDR3 region having the sequence of SEQ ID NO: 6; and a light chain variable domain that contains a LCDR1 region having the sequence of SEQ ID NO: 7, a LCDR2 region having the sequence of SEQ ID NO: 8, and a LCDR3 region having the sequence of SEQ ID NO: 9. The heavy chain variable domain comprises the sequence of SEQ ID NO: 2, and wherein the light chain variable domain comprises the sequence of SEQ ID NO: 3.Type: GrantFiled: December 13, 2019Date of Patent: July 23, 2024Assignee: DEVELOPMENT CENTER FOR BIOTECHNOLOGYInventors: Chen-Hsuan Ho, Chu-Bin Liao, Yu-Kai Chen, Chen-Wei Huang, Tze-Ping Yang, Szu-Liang Lai
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Patent number: 12044825Abstract: A four-piece optical image capturing system. In order from an object side to an image side, the optical image capturing system along the optical axis includes a first lens with positive refractive power; a second lens with refractive power; a third lens with refractive power; and a fourth lens with refractive power; and at least one of the image-side surface and object-side surface of each of the four lenses are aspheric. The optical image capturing system can increase aperture value and improve the imagining quality for use in compact cameras.Type: GrantFiled: October 18, 2021Date of Patent: July 23, 2024Assignee: Ability Opto-Electroncis Technology Co., Ltd.Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Yao-Wei Liu
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Patent number: 12044847Abstract: A vehicle auxiliary system includes at least three optical image capturing systems respectively disposed on a left portion, a right portion, and a rear portion of a movable carrier, at least one image fusion output device, and at least one displaying device. Each optical image capturing system includes an image capturing module and an operation module. The operation module is electrically connected to the image capturing module. The image fusion output device disposed inside the movable carrier is electrically connected to the optical image capturing systems. The displaying device is electrically connected to the image fusion output device. Each optical image capturing system has at least one lens group. The lens group includes at least two lenses having refractive power and satisfies: 1.0?f/HEP?10.0; 0 deg<HAF?150 deg; and 0.9?2(ARE/HEP)?2.0.Type: GrantFiled: January 6, 2023Date of Patent: July 23, 2024Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTDInventors: Yeong-Ming Chang, Chien-Hsun Lai, Yao-Wei Liu
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Publication number: 20240239059Abstract: A molding method of a support rod that first passing a plurality of long fibers through a resin bath for impregnating with resin, then passing the plurality of long fibers impregnated with resin through a bundling hole of a position-constrained vertical plate on a machine to preliminarily form a bundle end; providing a coating layer on the machine, one end of the coating layer obliquely passes through a guiding portion on the position-constrained vertical plate to downwardly contact the bundle end; then placing the one end of the coating layer and the bundle end into a mold cavity of a mold at the same time to form a long rod body; and then cutting the long rod body into multi-segment support rods through a cutting process.Type: ApplicationFiled: May 17, 2023Publication date: July 18, 2024Inventors: Che-Yuan Liu, Chang-Hsing Lee, Ming-Chuan Liu, Zhao-Xu Lai, Pen-Chien Yu, Shu-Fen Wang, Chia-Chang Hsu, Ren-Wei Tsai, Zong-You Chen, Da-Chun Chien
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Publication number: 20240238432Abstract: A method for modifying glycoproteins is provided. The present disclosure also provides a method for producing glycoprotein-payload conjugates, the conjugates produced thereby, and the use thereof.Type: ApplicationFiled: December 29, 2023Publication date: July 18, 2024Inventors: Shih-Hsien CHUANG, Yu-Wei LAI, Cheng-Chou YU, Shu-Ping YEH, Jin-Yu WANG, Shih-Chong TSAI, Wei-Ting SUN, Chin-Yi Huang
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Publication number: 20240194682Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.Type: ApplicationFiled: January 22, 2024Publication date: June 13, 2024Applicant: Tiawan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien WU, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
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Publication number: 20240189292Abstract: The present invention relates to a series of substituted pyridine-2,4-dione derivatives and preparation methods therefor, and in particular, to a compound represented by formula (I) and a pharmaceutically acceptable salt thereof.Type: ApplicationFiled: February 25, 2022Publication date: June 13, 2024Inventors: Xiaobing YAN, Wei LAI, Charles Z. DING, Shuhui CHEN
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Publication number: 20240178139Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.Type: ApplicationFiled: February 8, 2024Publication date: May 30, 2024Inventors: Wei-An LAI, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
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Publication number: 20240178214Abstract: An integrated circuit includes a horizontal routing track in a first metal layer, and a backside routing track in a backside metal layer. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. The horizontal routing track is conductively connected to a first terminal of a first transistor without passing through a routing track in another metal layer. The backside routing track is conductively connected to a second terminal of the first transistor without passing through a routing track in another metal layer. One of the first terminal and the second terminal is a gate terminal of the first transistor while another one the first terminal and the second terminal is either a source terminal or a drain terminal of the first transistor.Type: ApplicationFiled: February 1, 2024Publication date: May 30, 2024Inventors: Wei-An LAI, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
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Publication number: 20240173080Abstract: A navigation system of a surgical robot includes an endoscope and a navigation device. The endoscope is configured to capture an internal image of a tissue. The navigation device is configured for: analyzing the internal image to obtain a depth information of the tissue; determining whether there are several passages in the tissue according to the depth information; and selecting the passage that conforms to a path planning setting when the passages appear in the tissue.Type: ApplicationFiled: December 28, 2022Publication date: May 30, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Po-Kai WANG, Tseng-Wei LAI
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Patent number: 11990477Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.Type: GrantFiled: September 24, 2020Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
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Publication number: 20240159878Abstract: A range detection device and a method for range detection thereof are disclosed. An optical sensing element receives a reflected signal of external light signal for triggering a transformation element to generate an electrical signal of receiving detection. Range detection data are generated to an operation processing unit according to the electrical signal of receiving detection and an electrical signal of reference. A plurality of first item data of the range detection data are compressed and operated to generate a plurality of first operation data to be stored as stored data. Further, the first item data correspond to a plurality of first storage addresses. The first operation data correspond to a plurality of second storage addresses. A first address amount of the first storage addresses is greater than a second address amount of the second storage addresses. Thereby, more storage addresses will be spared and hence extending the detection range.Type: ApplicationFiled: November 14, 2023Publication date: May 16, 2024Inventor: Chih-Wei Lai
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Publication number: 20240142546Abstract: Disclosed is a method for testing and evaluating a short-circuit withstand capability of a press-pack power component.Type: ApplicationFiled: October 11, 2023Publication date: May 2, 2024Inventors: Hui LI, Renkuan LIU, Ran YAO, Wei LAI, Zeyu DUAN, Zheyan ZHU, Bailing ZHOU, Siyu CHEN, Jinyuan LI, Zhongyuan CHEN
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Publication number: 20240105601Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Wei-An LAI, Te-Hsin CHIU, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG, Chia-Tien WU
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Patent number: 11942469Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.Type: GrantFiled: June 10, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-An Lai, Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng, Chung-Hsing Wang
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Publication number: 20240094559Abstract: A contact lens includes a central region, an annular region and a peripheral region. The central region includes a central point of the contact lens. The annular region symmetrically surrounds the central region. The peripheral region symmetrically surrounds the annular region. The peripheral region includes at least one color pattern portion. The annular region includes at least one power of critical point.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: En-Ping LIN, I-Wei LAI, Chun-Hung TENG
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Publication number: 20240088049Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a first chip, a second chip, a conductive substrate, a dielectric layer, a vertical conductive structure, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The vias penetrate through the substrate, and a part of the vias is disposed in a first die-bonding region and a second die-bonding region. The electrodes extend from the first board surface to the second board surface through the vias. The dielectric layer is formed on the substrate to cover a lower electrode portion of each of the electrodes. The vertical conductive structure is formed to be partially embedded into the dielectric layer and provide an electrical path between the first and second die-bonding regions. The dam is formed to surround the first and the second die-bonding regions.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: DEI-CHENG LIU, JHIH-WEI LAI
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Patent number: 11923297Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.Type: GrantFiled: April 27, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng
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Patent number: 11923369Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.Type: GrantFiled: February 25, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Hsin Chiu, Wei-Cheng Lin, Wei-An Lai, Jiann-Tyng Tzeng
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Publication number: 20240071776Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.Type: ApplicationFiled: December 2, 2022Publication date: February 29, 2024Inventors: DEI-CHENG LIU, CHIA-SHUAI CHANG, MING-YEN PAN, JIAN-YU SHIH, JHIH-WEI LAI, SHIH-HAN WU