Patents by Inventor Wei-cheng Chen

Wei-cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220007936
    Abstract: The present invention provides a neurological disorders decision support system that can assist an examiner to diagnose an examinee. The neurological disorders decision support system includes a user module, a screening module, an intelligent calculation module and a diagnosis module. The user module sends an inquiry to the examinee, receives a response message from the examinee, and retrieves a physiological characteristic signal of the examinee. The screening module executes a neurological examination application program to indicate to the examinee to obtain physiological characteristic signals. The screening module outputs response messages and physiological characteristic signals for the intelligent calculation module to execute an algorithm to generate an analysis report. The analysis report assists the examiner for diagnosis, and sends a diagnosis notification to the user module through the diagnosis module. The invention also provides a neurological disorders decision support method.
    Type: Application
    Filed: July 13, 2020
    Publication date: January 13, 2022
    Inventors: Chun-Chen YANG, Ching-Fu WANG, Chin-Hsun HUANG, Wei-Cheng CHEN
  • Patent number: 11217139
    Abstract: A gate scanning unit circuit is applied in a display panel including a number of gate lines and a driver configured to output clock signals. The gate scanning unit circuit is configured to scan the number of gate lines. The gate scanning unit circuit includes a flip-flop and at least two output units. The flip-flop is configured to output a trigger signal. Each output unit is connected to the flip-flop and the driver. Each of the at least two output units is connected to the number of gate lines one-to-one. The output unit is configured to output a gate scan signal to the corresponding connected gate line according to the trigger signal and the clock signals.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 4, 2022
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hideo Sato, Mitsuru Goto, Wei-Cheng Chen, Chun-Jung Shih
  • Patent number: 11081371
    Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 3, 2021
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Publication number: 20210215982
    Abstract: An array substrate which can carry a camera in a camera area seamlessly surrounded by a display area is disclosed, the camera area defines a transparent area, a first routing area adjacent to the transparent area, and a second routing area surrounding the first routing area. The array substrate includes a first substrate, a first conductive layer, a second conductive layer, a common electrode layer, a third conductive layer, a planarization layer, and a photo spacer. The planarization layer in the transparent area is in direct contact with the first substrate. The photo spacer is in the first routing area. The third conductive layer is around the transparent area and the first routing area.
    Type: Application
    Filed: April 24, 2020
    Publication date: July 15, 2021
    Inventors: SHIANG-RUEI OUYANG, WEI-CHENG CHEN
  • Publication number: 20210215983
    Abstract: An array substrate carrying a display area and a camera area surrounded by the display area provides connections to both areas free of electrical interference. The camera area includes a transparent area and a routing area surrounding the transparent area. The array substrate includes a first conductive layer and a second conductive layer. The first conductive layer includes first wires and first capacitance compensation patterns. The second conductive layer includes second wires. Each first capacitance compensation pattern is between adjacent first wires. Along a thickness direction of the array substrate, a projection of each first capacitance compensation pattern on the substrate overlaps with a projection of at least one second wire. A display panel and a display device are also disclosed.
    Type: Application
    Filed: April 24, 2020
    Publication date: July 15, 2021
    Inventors: SHIANG-RUEI OUYANG, WEI-CHENG CHEN
  • Publication number: 20210105390
    Abstract: A camera module includes a circuit board, an image sensor, a filter removable switch, a camera lens, and a thermally conductive structure. The circuit board has a surface. The image sensor is disposed on the surface. The filter removable switch is located over the surface. The camera lens is on the light-sensing path of the image sensor. The thermally conductive structure is contacted between the circuit board and the filter removable switch and has a channel. The image sensor is located in the channel.
    Type: Application
    Filed: March 9, 2020
    Publication date: April 8, 2021
    Inventors: Wei-Cheng CHEN, Tsung-You WANG
  • Patent number: 10962851
    Abstract: A display area for displaying images and a camera area surrounded by the display area are both founded on an array substrate. The camera area defines a transparent area and a wire-routing area surrounding the transparent area. The array substrate includes first data lines, second data lines, and first scan lines. Each first data line, each second data line, and each first scan line avoid the transparent area and cross the wire-routing area. Each second data line includes an auxiliary data line and a data line lead. The first scan lines and the auxiliary data lines are defined by a first conductive layer, the first data lines and the data line leads are defined in a second conductive layer insulated and spaced from the first conductive layer, such a stacked arrangement allows an optically-clear path for the camera to collect light.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 30, 2021
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Shiang-Ruei Ouyang, Wei-Cheng Chen
  • Patent number: 10890794
    Abstract: A device with a display uninterrupted by a camera includes a display panel and the camera. The display device defines a display area for displaying images and a light transmission area surrounded by the display area. The camera is in the light transmission area and can collect light for images through the light transmission area.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 12, 2021
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hao-Ting Tien, I-Wei Chen, Wei-Cheng Chen
  • Publication number: 20200312211
    Abstract: A gate scanning unit circuit is applied in a display panel including a number of gate lines and a driver configured to output clock signals. The gate scanning unit circuit is configured to scan the number of gate lines. The gate scanning unit circuit includes a flip-flop and at least two output units. The flip-flop is configured to output a trigger signal. Each output unit is connected to the flip-flop and the driver. Each of the at least two output units is connected to the number of gate lines one-to-one. The output unit is configured to output a gate scan signal to the corresponding connected gate line according to the trigger signal and the clock signals.
    Type: Application
    Filed: September 23, 2019
    Publication date: October 1, 2020
    Inventors: HIDEO SATO, MITSURU GOTO, WEI-CHENG CHEN, CHUN-JUNG SHIH
  • Patent number: 10756077
    Abstract: A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 25, 2020
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Patent number: 10701807
    Abstract: A multi-layered circuit board structure includes a first circuit board, a second circuit board, and a heat dissipation plate. The first circuit board includes a first surface. The second circuit board includes a second surface facing the first surface. The heat dissipation plate is located between the first circuit board and the second circuit board. The heat dissipation plate includes a substrate and a fixing base integrally extending from the substrate and bent. The fixing base includes a connecting plate, a first plate, and a second plate spaced apart from the first plate. The connecting plate is connected between the first plate and the second plate. The first surface is bonded to a surface of the first plate, the second surface is bonded to a surface of the second plate, and the substrate is in contact with neither the first surface nor the second surface.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: June 30, 2020
    Assignee: CHICONY ELECTRONICS CO., LTD.
    Inventors: Wei-Cheng Chen, Jin-Kae Jang
  • Publication number: 20200174301
    Abstract: A device with a display uninterrupted by a camera includes a display panel and the camera. The display device defines a display area for displaying images and a light transmission area surrounded by the display area. The camera is in the light transmission area and can collect light for images through the light transmission area.
    Type: Application
    Filed: September 18, 2019
    Publication date: June 4, 2020
    Inventors: HAO-TING TIEN, I-WEI CHEN, WEI-CHENG CHEN
  • Publication number: 20200113052
    Abstract: A multi-layered circuit board structure includes a first circuit board, a second circuit board, and a heat dissipation plate. The first circuit board includes a first surface. The second circuit board includes a second surface facing the first surface. The heat dissipation plate is located between the first circuit board and the second circuit board. The heat dissipation plate includes a substrate and a fixing base integrally extending from the substrate and bent. The fixing base includes a connecting plate, a first plate, and a second plate spaced apart from the first plate. The connecting plate is connected between the first plate and the second plate. The first surface is bonded to a surface of the first plate, the second surface is bonded to a surface of the second plate, and the substrate is in contact with neither the first surface nor the second surface.
    Type: Application
    Filed: February 5, 2019
    Publication date: April 9, 2020
    Inventors: Wei-Cheng Chen, Jin-Kae Jang
  • Patent number: 10504847
    Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 10, 2019
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Patent number: 10459007
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 29, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Publication number: 20190139952
    Abstract: A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.
    Type: Application
    Filed: December 14, 2017
    Publication date: May 9, 2019
    Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Publication number: 20190139898
    Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.
    Type: Application
    Filed: December 14, 2017
    Publication date: May 9, 2019
    Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Patent number: 10277045
    Abstract: The present invention discloses an electronic device charger, mainly comprising: a voltage converting module, a microprocessor, a low voltage detecting unit, and an over voltage sensing unit. When a rated output voltage of a vehicle battery of an electric vehicle is detected to be lower than a first threshold voltage by the low voltage detecting unit or found to be higher than a second threshold voltage by the over voltage sensing unit, the microprocessor immediately stops the vehicle battery providing electrical power to at least one portable electronic device owned by the driver of the electric vehicle. Therefore, the electronic device charger can not only save the energy of the vehicle battery while the vehicle battery is at a low voltage state, but also protect the portable electronic devices from being damaged by the electrical power as the rated output voltage of the vehicle battery exceed a normal voltage level.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 30, 2019
    Assignees: SOLTEAM ELECTRONICS (DONG GUAN) CO., LTD., SOLTEAM ELECTRONICS (SU ZHOU) CO., LTD., SOLTEAM ELECTRONICS CO., LTD.
    Inventors: Ping-Lung Lee, Wei-Cheng Chen, Jen-Tseng Huang, Chin-Cheng Lu
  • Publication number: 20190120875
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Applicant: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10184956
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 22, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen