Patents by Inventor Wei Cheng Hsu
Wei Cheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12224485Abstract: A microminiaturized antenna feed module includes a substrate, a plurality of coupled feed portions, and an active circuit. The substrate defines a plurality of visa penetrating the substrate. The coupled feed portions, made of conductive material and have different coupling areas, are electrically connected to the active circuit through the holes, to feed in electrical signals, the coupled feed portions couple the electrical signals to the metal frame to radiate wireless signals; the active circuit controls the switching of radiation modes of the metal frame. The application also provides an electronic device with the microminiaturized antenna feed module.Type: GrantFiled: May 31, 2022Date of Patent: February 11, 2025Assignee: FIH CO., LTD.Inventors: Cho-Kang Hsu, Min-Hui Ho, Wei-Cheng Su, Yen-Hui Lin
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Publication number: 20250040157Abstract: A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.Type: ApplicationFiled: October 26, 2023Publication date: January 30, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Liang Hsu, Chung-Lei Chen, Anhao Cheng, Yen-Liang Lin, Ru-Shang Hsiao
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Patent number: 12191336Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.Type: GrantFiled: May 23, 2022Date of Patent: January 7, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Jui Wang, Dun-Nian Yaung, Chen-Jong Wang, Ming-Chieh Hsu, Wei-Cheng Hsu, Yuichiro Yamashita
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Publication number: 20240379796Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
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Publication number: 20240361612Abstract: A head mounted display device includes a host, two sliding parts, two locking parts and two brackets. The host has two connecting bases located on opposite sides of the host. The two sliding parts are respectively slidably connected to the corresponding connecting base. The two locking parts are respectively used to lock the corresponding sliding part in a retracted position or a pulled-out position relative to the corresponding connecting base. The two brackets are respectively pivotally connected to one end of the corresponding sliding part away from the host.Type: ApplicationFiled: November 10, 2023Publication date: October 31, 2024Applicant: HTC CorporationInventors: Sheng-Wen Chen, Wei-Cheng Hsu
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Publication number: 20240355859Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first IC chip includes a plurality of photodetectors disposed in a first substrate and a first bond structure. The first bond structure includes a first plurality of bond contacts disposed on a first plurality of conductive bond pads. The second IC chip includes a second bond structure and a second substrate. A first bond interface is disposed between the first bond structure and the second bond structure. The second bond structure comprises a second plurality of bond contacts. The first bond structure further includes a first plurality of shield structures disposed between adjacent conductive bond pads in the first plurality of conductive bond pads.Type: ApplicationFiled: April 19, 2023Publication date: October 24, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240347576Abstract: Various embodiments of the present disclosure relate to an interstitial stacked-integrated-circuit interface shielding structure. A first integrated circuit (IC) chip includes a first dielectric layer. A second IC chip is bonded to the first IC chip at a bond interface and includes a second dielectric layer directly contacting the first dielectric layer at the bond interface. A first pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. A second pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. A pair of shield structures are respectively in the first and second dielectric layers and directly contact at the bond interface. Further, the pair of shield structures separate the first pair of conductive pads from the second pair of conductive pads.Type: ApplicationFiled: April 17, 2023Publication date: October 17, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240339475Abstract: Some embodiments relate to an IC device, including a first chip; and a second chip bonded to the first chip at a bonding interface; where the first and second chips respectively comprise a first dielectric layer and a second dielectric layer directly contacting; the first chip further comprises a plurality of conductive pads recessed into the first dielectric layer and in a plurality of rows and columns; where the plurality of conductive pads are arranged with a zig-zag layout along the plurality of columns and along the plurality of rows and comprise a first conductive pad and a second conductive pad; the first chip further comprises a first shield line in the first dielectric layer and laterally between the first and second conductive pads, and the second chip further comprises a contact recessed into the second dielectric layer and directly contacting the first conductive pad at the bonding interface.Type: ApplicationFiled: April 7, 2023Publication date: October 10, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240339467Abstract: Some embodiments relate to an IC device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.Type: ApplicationFiled: April 7, 2023Publication date: October 10, 2024Inventors: Chi-Hsien Chung, Tzu-Jui Wang, Chia-Chi Hsiao, Kuan-Chieh Huang, Wei-Cheng Hsu, Hao-Lin Yang, Yi-Han Liao, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240332333Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first chip IC includes a first bond structure. The first bond structure includes a first plurality of conductive bond pads and a first plurality of shield structures disposed between adjacent conductive bond pads among the first plurality of conductive bond pads. The second IC chip includes a second bond structure. A bonding interface is disposed between the first bond structure and the second bond structure. The second bond structure includes a second plurality of conductive bond pads and a second plurality of shield structures. The first plurality of conductive bond pads contacts the second plurality of conductive bond pads and the first plurality of shield structures contacts the second plurality of shield structures at the bonding interface.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240313010Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.Type: ApplicationFiled: May 31, 2024Publication date: September 19, 2024Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
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Patent number: 12094948Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.Type: GrantFiled: September 3, 2021Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
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Patent number: 12057486Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.Type: GrantFiled: March 13, 2023Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Yen-Ju Chen
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Patent number: 12040336Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.Type: GrantFiled: December 9, 2022Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
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Publication number: 20240128216Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.Type: ApplicationFiled: January 4, 2023Publication date: April 18, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Ching-Chun Wang, Hsiao-Hui Tseng, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240096918Abstract: A device structure according to the present disclosure may include a first die having a first substrate and a first interconnect structure, a second die having a second substrate and a second interconnect structure, and a third die having a third interconnect structure and a third substrate. The first interconnect structure is bonded to the second substrate via a first plurality of bonding layers. The second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers. The third substrate includes a plurality of photodiodes and a first transistor. The second die includes a second transistor having a source connected to a drain of the first transistor, a third transistor having a gate connected to drain of the first transistor and the source of the second transistor, and a fourth transistor having a drain connected to the source of the third transistor.Type: ApplicationFiled: January 17, 2023Publication date: March 21, 2024Inventors: Hao-Lin Yang, Tzu-Jui Wang, Wei-Cheng Hsu, Cheng-Jong Wang, Dun-Nian Yuang, Kuan-Chieh Huang
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Publication number: 20240079434Abstract: Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures.Type: ApplicationFiled: January 5, 2023Publication date: March 7, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung, Yu-Chun Chen
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Publication number: 20230319418Abstract: A head-mounted display device and a control method for an eye-tracking operation are provided. The head-mounted display device includes a frame, a track, a sensor and a controller. The track is disposed on a peripheral region of the frame. The sensor is disposed on the track, and is configured to capture a target image of a target area. The controller is coupled to the sensor, is configured to generate a control signal according to the target image, and adjust a position of the sensor on the peripheral region by moving the sensor according to the control signal.Type: ApplicationFiled: January 3, 2023Publication date: October 5, 2023Applicant: HTC CorporationInventors: Yan-Min Kuo, Jun-Lin Guo, Wei-Chen Chen, Chih-Lin Chang, Wei-Cheng Hsu, Cheng-Yu Chen
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Publication number: 20230305296Abstract: A head-mounted display device includes a body, an eye tracking module and a face gasket. The body has a first lens and a second lens corresponding to both eyes, and also has a first positioning portion. The eye tracking module is assembled to and electrically connected to the body and includes an outer frame, a first camera, a second camera, a first lens frame and a second lens frame. The outer frame has a second positioning portion. The second positioning portion is used for connecting with the first positioning portion, so that the outer frame is positioned on the body. The first lens frame and the second lens frame are movably arranged on the outer frame. The first lens frame is used for connecting the first lens. The second lens frame is used for connecting the second lens. The first camera is arranged on the first lens frame. The second camera is arranged on the second lens frame. The first camera and the second camera are used to shoot both eyes.Type: ApplicationFiled: July 28, 2022Publication date: September 28, 2023Applicant: HTC CorporationInventors: Wei-Cheng Hsu, Cheng-Yu Chen, Syuan-He Shih, Chih-Lin Chang
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Publication number: 20230290824Abstract: A method for forming a semiconductor device structure includes forming first nanostructures and second nanostructures over a substrate. The method also includes forming a first metal gate layer surrounding the first nanostructures and over the first nanostructures and the second nanostructures. The method also includes etching back the first metal gate layer over the first nanostructures and the second nanostructures. The method also includes removing the first metal gate layer over the second nanostructures. The method also includes forming a second metal gate layer surrounding the second nanostructures and over the first nanostructures and the second nanostructures.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yao YANG, Chia-Wei CHEN, Wei-Cheng HSU, Jo-Chun HUNG, Yung-Hsiang CHAN, Hui-Chi CHEN, Yen-Ta LIN, Te-Fu YEH, Yun-Chen WU, Yen-Ju CHEN, Chih-Ming SUN