Patents by Inventor Wei Cheng Lin

Wei Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210376171
    Abstract: An optical sensor includes a substrate, a first/second/third well disposed in a sensing region, a deep trench isolation structure, and a passivation layer. The substrate has a first conductivity type and includes the sensing region. The first well has a second conductivity type and a first depth. The second well has the second conductivity type and a second depth. The third well has the first conductivity type and a third depth. The deep trench isolation structure is disposed in the substrate and surrounding the sensing region, wherein the depth of the deep trench isolation structure is greater than the first depth, the first depth is greater than the second depth, and the second depth is greater than the third depth. The passivation layer is disposed over the substrate, wherein the passivation layer includes a plurality of protruding portions disposed directly above the sensing region.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shih-Hao LIU, Chung-Ren LAO, Chih-Cherng LIAO, Wu-Hsi LU, Ming-Cheng LO, Wei-Lun CHUNG, Chih-Wei LIN
  • Publication number: 20210373430
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.
    Type: Application
    Filed: November 24, 2020
    Publication date: December 2, 2021
    Inventors: Hung-Yi TSAI, Wei-Che HSIEH, Ta-Cheng LIEN, Hsin-Chang LEE, Ping-Hsun LIN, Hao-Ping CHENG, Ming-Wei CHEN, Szu-Ping TSAI
  • Publication number: 20210375775
    Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Publication number: 20210367042
    Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Chun-Hsien Huang, Chang-Ting Chung, Wei-Cheng Lin, Wei-Jung Lin, Chih-Wei Chang
  • Publication number: 20210343733
    Abstract: A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventors: Meng-Han LIN, Wei Cheng WU
  • Publication number: 20210343734
    Abstract: A device has a semiconductor substrate including a recessed region. The recessed region has a center portion and a periphery portion. An isolation region abuts the periphery portion. A plurality of gate stacks are in the recessed region. A protective layer overlying the plurality of gate stacks and the isolation region has a substantially planar upper surface across the recessed region and the isolation region.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventors: Meng-Han LIN, Wei Cheng WU
  • Publication number: 20210343744
    Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.
    Type: Application
    Filed: February 25, 2021
    Publication date: November 4, 2021
    Inventors: Te-Hsin CHIU, Wei-Cheng LIN, Wei-An LAI, Jiann-Tyng TZENG
  • Publication number: 20210333717
    Abstract: A method of fabricating a mask is provided. The method includes providing a hard mask layer disposed on top of absorber, a capping layer, and a multilayer that are disposed on a substrate. The method includes forming a middle layer over the hard mask layer, forming a photo resist layer over the middle layer, patterning the photo resist layer, etching the middle layer through the patterned photo resist layer, etching the hard mask layer through the patterned middle layer, and etching the absorber through the patterned hard mask layer. In some embodiments, etching the hard mask layer through the patterned middle layer includes a dry-etching process that has a first removal rate of the hard mask layer and a second removal rate of the middle layer, and a ratio of the first removal rate of the hard mask layer to the second removal rate of the middle layer is greater than 5.
    Type: Application
    Filed: October 30, 2020
    Publication date: October 28, 2021
    Inventors: Wei-Che HSIEH, Tzu-Yi WANG, Ping-Hsun LIN, Ta-Cheng LIEN, Hsin-Chang LEE, Huan-Ling LEE
  • Publication number: 20210320052
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Wei-Tao Tsai
  • Publication number: 20210313263
    Abstract: A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: WEI-AN LAI, WEI-CHENG LIN, JIANN-TYNG TZENG
  • Publication number: 20210313376
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen
  • Publication number: 20210314690
    Abstract: An electronic device including a display panel, a protection layer, and a sound broadcasting element is provided. The display panel is disposed on an inner surface of the protection layer. The sound broadcasting element is disposed on the inner surface of the protection layer and includes a piezoelectric component and a connection component. The connection component is located on a side of the display panel, the connection component contacts the protection layer and is connected between the piezoelectric component and the protection layer. A back surface of the display panel is located between the piezoelectric component and the protection layer, wherein the back surface of the display panel is a surface away from the protection layer.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Applicant: Innolux Corporation
    Inventors: Tzu-Pin Hsiao, Wei-Cheng Lee, Jiunn-Shyong Lin, I-An Yao
  • Publication number: 20210313325
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 7, 2021
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Patent number: 11133254
    Abstract: An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-An Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Publication number: 20210296313
    Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.
    Type: Application
    Filed: December 22, 2020
    Publication date: September 23, 2021
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching
  • Publication number: 20210285946
    Abstract: A strip detecting apparatus includes a black box, a light guide plate disposed on the black box, a light source, an optical calibration platform, a strip platform, a test strip contained in the strip platform, an image capturing device and an image processing device. The light source is disposed on the black box to emit light toward the black box via the light guide plate. The image capturing device is disposed on the black box for respectively capturing an optical calibration image and a detection image when the optical calibration platform and the strip platform are inserted into the black box respectively. The image processing device is coupled to the image capturing device for calibrating relationship information between the concentration and the grayscale value of the test strip according to the optical calibration image and for generating a test result according to the calibrated relationship information and the detection image.
    Type: Application
    Filed: July 17, 2020
    Publication date: September 16, 2021
    Inventors: Yu-Cheng Lin, Wei-Chien Weng, Kai-Wen Lin
  • Patent number: 11121261
    Abstract: A semiconductor substrate includes a substrate, a first metal oxide semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a second metal oxide semiconductor layer. The first transistor includes a first metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a first gate of the first conductive layer, a first source of the second conductive layer, and a first drain of the second conductive layer. The second transistor includes a second metal oxide semiconductor pattern of the first metal oxide semiconductor layer, a second gate of the first conductive layer, a second source of the second conductive layer, a second drain of the second conductive layer, and a third metal oxide semiconductor pattern of the second metal oxide semiconductor layer.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 14, 2021
    Assignee: Au Optronics Corporation
    Inventors: Wei-Ting Lin, Dean Wang, Chun-Cheng Cheng
  • Patent number: 11121256
    Abstract: A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Liang Chen, Lei-Chun Chou, Jack Liu, Kam-Tou Sio, Hui-Ting Yang, Wei-Cheng Lin, Chun-Hung Liou, Jiann-Tyng Tzeng, Chew-Yuen Young
  • Publication number: 20210280579
    Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Te LIN, Wei-Yuan LU, Feng-Cheng YANG
  • Publication number: 20210280694
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 9, 2021
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu