Patents by Inventor Wei Cheng Lin

Wei Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12243930
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Tai Chang, Tung-Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Publication number: 20250070092
    Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Wen-Tuo Huang, Chia-Sheng Lin, Wei Chuang Wu, Shih Kuang Yang, Chung-Jen Huang, Shun-Kuan Lin, Chien Lin Liu, Ping-Tzu Chen, Yung Chun Tu
  • Patent number: 12237382
    Abstract: A semiconductor device includes: a substrate; a channel layer disposed on the substrate, wherein the channel layer is made of GaN; a barrier layer disposed on the channel layer, wherein the barrier layer is made of AlzGa1-zN; and an inserting structure inserted between the channel layer and the barrier layer. The inserting structure includes: a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of AlxGa1-xN; and a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of AlyGa1-yN, and y is greater than x. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; and a spike region formed below at least one of the source electrode and the drain electrode.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: February 25, 2025
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chieh-Chih Huang, Yan-Cheng Lin, Cheng-Kuo Lin, Wei-Chou Wang, Che-Kai Lin, Jiun-De Wu
  • Patent number: 12237418
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Publication number: 20250063813
    Abstract: A semiconductor device includes a first well region laterally separated from a second well region in a substrate, a shallow trench isolation (STI) structure laterally between the first well region and the second well region in the substrate, a first implant region of a dopant type opposite to a dopant type of the first well region in the substrate, disposed vertically lower than the STI structure and laterally between the first well region and a lateral center of the STI structure, and a second implant region of a dopant type opposite to a dopant type of the second well region in the substrate, disposed vertically lower than the STI structure and laterally between the second well region and the lateral center of the STI structure.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hsuan Peng, Wei-Lun Chung, Anhao Cheng, Chien-Wei Lee, Yen-Liang Lin, Ru-Shang Hsiao
  • Patent number: 12225973
    Abstract: A method for manufacturing a recycled carbon fiber underlay, which mixes recycled carbon fiber material with nylon or composite plastic and forms an elastic recycled carbon fiber injection particle material, and under an injection process condition, the recycled carbon fiber injection particle material is injected and molded into a recycled carbon fiber underlay. The recycled carbon fiber arch insole comprises a recycled carbon fiber underlay manufactured by the aforementioned manufacturing method, together with the data of podiatric medical big numeric database of human factors engineering for the innovative design of mechanical insole products and the application development of recycled materials to encourage recycling to reduce carbon emissions, while improving the function, durability, and comfort of insole inserts.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: February 18, 2025
    Assignee: DR. FOOT TECHNOLOGY CO., LTD.
    Inventor: Wei-Cheng Lin
  • Patent number: 12230554
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Wei-Tao Tsai
  • Publication number: 20250054662
    Abstract: The present invention relates to a thermistor paste and a manufacturing method thereof. The thermistor paste includes specific contents of thermistor powder, a glass powder, and an organic carrier, in which the organic carrier includes an organic solvent, a binder, and an additive. A thermistor semi-finished product slurry of the present invention has been sintered. The thermistor paste of the present invention excludes a precious metal, such as ruthenium, gold, or platinum, etc., so the production cost can be reduced.
    Type: Application
    Filed: November 27, 2023
    Publication date: February 13, 2025
    Inventors: Shen-Li HSIAO, Kuang-Cheng LIN, Wei-Chen HUANG, Ren-Hong WANG
  • Publication number: 20250056819
    Abstract: A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: February 13, 2025
    Inventors: Wei-Lun Chung, Chung-Lei Chen, Anhao Cheng, Chien-Wei Lee, Yen-Liang Lin, Ru-Shang Hsiao
  • Patent number: 12224247
    Abstract: A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
    Type: Grant
    Filed: March 26, 2024
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Patent number: 12224485
    Abstract: A microminiaturized antenna feed module includes a substrate, a plurality of coupled feed portions, and an active circuit. The substrate defines a plurality of visa penetrating the substrate. The coupled feed portions, made of conductive material and have different coupling areas, are electrically connected to the active circuit through the holes, to feed in electrical signals, the coupled feed portions couple the electrical signals to the metal frame to radiate wireless signals; the active circuit controls the switching of radiation modes of the metal frame. The application also provides an electronic device with the microminiaturized antenna feed module.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 11, 2025
    Assignee: FIH CO., LTD.
    Inventors: Cho-Kang Hsu, Min-Hui Ho, Wei-Cheng Su, Yen-Hui Lin
  • Publication number: 20250044708
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun LIU, Huicheng CHANG, Chia-Cheng CHEN, Jyu-Horng SHIEH, Liang-Yin CHEN, Shu-Huei SUEN, Wei-Liang LIN, Ya Hui CHANG, Yi-Nien SU, Yung-Sung YEN, Chia-Fong CHANG, Ya-Wen YEH, Yu-Tien SHEN
  • Publication number: 20250046367
    Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.
    Type: Application
    Filed: February 20, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kao-Cheng Lin, Yen-Huei Chen, Wei Min Chan, Hidehiro Fujiwara, Wei-Cheng Wu, Pei-Yuan Li, Chien-Chen Lin, Shang Lin Wu
  • Publication number: 20250048658
    Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; an interconnect structure disposed over the substrate, the interconnect structure including an dielectric; a first bottom electrode structure disposed in the dielectric, the first bottom electrode structure having a first width as measured between outer sidewalls of the first bottom electrode structure and a first depth as measured from an upper surface of the dielectric; and a second bottom electrode structure disposed in the dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width as measured between outer sidewalls of the second bottom electrode structure and a second depth as measured from the upper surface of the dielectric; where the first width is greater than the second width and the first depth is greater than the second depth.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Wei-Chih Weng, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 12218050
    Abstract: A method for fabricating a semiconductor structure includes depositing a first insulation material over a substrate, wherein the substrate includes an active region. The method further includes etching the first insulation material to define a first recess extending along a first direction at a first level of the first insulation material. The method further includes depositing a second insulation material lining with a sidewall of the first recess. The method further includes depositing a first metal line in the first recess.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Wei-An Lai, Meng-Hung Shen, Wei-Cheng Lin, Jiann-Tyng Tzeng, Kam-Tou Sio
  • Patent number: 12218141
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20250038071
    Abstract: An integrated circuit is provided, including a first transistor of a first conductivity type comprising first and second active regions, a second transistor of a second conductivity type comprising third and fourth active regions and arranged under the first transistor along a first direction, a first gate structure extending in the first direction and shared by the first and second transistors, an isolation layer sandwiched between the first and second transistors and extending along a second direction to pass through the first gate structure, and a connection layer surrounded by the isolation layer and extending along the second direction to pass through the first gate structure. The isolation layer has a first surface contacting the first and second active regions and a second surface contacting the third and fourth active regions. The connection layer comprises first and second portions are electrically coupled to the first and fourth active regions.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 30, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng TZENG, Shih-Wei PENG, Chun-Yen LIN, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20250040157
    Abstract: A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.
    Type: Application
    Filed: October 26, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Liang Hsu, Chung-Lei Chen, Anhao Cheng, Yen-Liang Lin, Ru-Shang Hsiao
  • Patent number: 12205634
    Abstract: The present disclosure provides an electronic circuit, a memory device, and a method for operating an electronic circuit. An electronic circuit comprises a driver circuit configured to provide a drive voltage to a word line of the electronic circuit, a suppression circuit electrically connected to the driver circuit and the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in the drive voltage. The control circuit controls the suppression circuit.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Cheng Wu, Pei-Yuan Li, Kao-Cheng Lin, Chien Hui Huang, Yung-Ning Tu
  • Publication number: 20250024671
    Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Hui Huang, Kao-Cheng LIN, Wei Min CHAN, Shang Lin WU, Chia-Chi HUNG, Wei-Cheng WU, Chia-Che CHUNG, Pei-Yuan LI, Chien-Chen LIN, Yung-Ning TU, Yen Lin CHUNG