Patents by Inventor Wei Cheng Lin

Wei Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384403
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Tung-Kai LIU, Tsau-Hua HSIEH, Wei-Cheng CHU, Chun-Hsien LIN, Chandra LIUS, Ting-Kai HUNG, Kuan-Feng LEE, Ming-Chang LIN, Tzu-Min YAN, Hui-Chieh WANG
  • Patent number: 11514707
    Abstract: Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Cheng Jhang, Han-Zong Pan, Wei-Ding Wu, Jui-Chun Weng, Hsin-Yu Chen, Cheng-San Chou, Chin-Min Lin
  • Publication number: 20220374577
    Abstract: A method (of forming a semiconductor device) including forming cell regions (in alternating first and second rows having first and second heights) including forming a majority of the cell regions in the first rows including: limiting a height of the majority of the cell regions to be single-row cell regions that span corresponding single one of the first rows but do not extend therebeyond; and forming a minority of the cell regions correspondingly in at least the first rows including reducing widths of the multi-row cell regions to be smaller than comparable single-row cell regions; and expanding heights of the minority of the cell regions to be multi-row cell regions, each of the multi-row cell regions spanning a corresponding single first row and at least a corresponding second row such that cell region densities of the second rows are at least about forty percent.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 24, 2022
    Inventors: Wei-Cheng LIN, Hui-Ting YANG, Jiann-Tyng TZENG, Lipen YUAN, Wei-An LAI
  • Publication number: 20220367678
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Publication number: 20220362460
    Abstract: An infusion apparatus includes a fixture body, a tube socket and a buckling device. The fixture body has a first and a second ends along a first direction. The fixture body has a through hole. Two first protruding pieces are located at the second end along a second direction perpendicular with the first direction. The fixture body penetrates through and is slidable relative with the tube socket which has two grooves along the second direction. The buckling device includes a machine body and two hooking structures. The machine body has a mounting hole. The hooking structures are disposed at opposite sides of the mounting hole and respectively include a hook and a second protruding piece. The hooks buckle within the grooves. A shortest distance between the second protruding pieces is less than a longest distance between the first protruding pieces.
    Type: Application
    Filed: June 14, 2019
    Publication date: November 17, 2022
    Inventors: Shou-tien YIN, Hon-wing AU, Wei-cheng LIN, Chi-lin LEE, Yi-yu LEE
  • Publication number: 20220367201
    Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Chin-Yuan TSENG, Yu-Tien SHEN, Wei-Liang LIN, Chih-Ming LAI, Kuo-Cheng CHING, Shi-Ning JU, Li-Te LIN, Ru-Gun LIU
  • Publication number: 20220367498
    Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Publication number: 20220367266
    Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 17, 2022
    Inventors: Shu-Cheng Chin, Chih-Yi Chang, Wei Hsiang Chan, Chih-Chien Chi, Chi-Feng Lin, Hung-Wen Su
  • Publication number: 20220367182
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.
    Type: Application
    Filed: June 21, 2021
    Publication date: November 17, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Yu Cheng Lin, Wei-Chuang Lai
  • Publication number: 20220359470
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Publication number: 20220358275
    Abstract: One aspect of this description relates to a method for operating an integrated circuit (IC) manufacturing system. The method includes placing a first nano-sheet structure within a IC layout diagram. The first nano-sheet structure has a first width. The method includes abutting a second nano-sheet structure with the first nano-sheet structure. The second nano-sheet structure has a second width. The second width is less than the first width. The method includes generating and storing the IC layout diagram in a storage device.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Wei-Cheng Lin, Yan-Hao Chen, Jiann-Tyng Tzeng, Lipen Yuan, Hui-Zhong Zhuang, Yu-Xuan Huang
  • Publication number: 20220352060
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Publication number: 20220348956
    Abstract: Provided is a lentivirus packaging system, which comprises: a transfer plasmid comprising a nucleotide sequence of TAR-reserved-chimeric 5? long terminal repeat (LTR); at least one packaging plasmid comprising a nucleotide sequence encoding TAR RNA binding protein, a nucleotide sequence of rev gene, a nucleotide sequence of gag gene, and a nucleotide sequence of pol gene; and an envelope plasmid. Due to the expression of gene of TAR RNA binding protein by the packaging plasmids, the produced lentivirus has higher virus titer and can improve the transduction rate and the gene delivery efficiency during cell transduction. The present invention further provides a method of improving lentivirus production in a host cell, which comprises using the lentivirus packaging system to transfect the host cell. The present invention further provides a cell transduced by the lentivirus and a method of using the cell for treating cancer.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 3, 2022
    Inventors: Wei-Chi LIN, Ssu-Yu CHOU, Yao-Cheng YANG, Chien-Ting LIN, CHEN-LUNG LIN
  • Patent number: 11488971
    Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Publication number: 20220340407
    Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chuan TENG, Ching-Kai SHEN, Jung-Kuo TU, Wei-Cheng SHEN, Xin-Hua HUANG, Wei-Chu LIN
  • Publication number: 20220344255
    Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 27, 2022
    Inventors: Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Publication number: 20220336612
    Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.
    Type: Application
    Filed: December 10, 2021
    Publication date: October 20, 2022
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG, Chia-Pin LIN, Wei-Yang LEE, Yen-Sheng LU
  • Publication number: 20220328397
    Abstract: A method for fabricating a semiconductor structure includes depositing a first insulation material over a substrate, wherein the substrate includes an active region. The method further includes etching the first insulation material to define a first recess extending along a first direction at a first level of the first insulation material. The method further includes depositing a second insulation material lining with a sidewall of the first recess. The method further includes depositing a first metal line in the first recess.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 13, 2022
    Inventors: Te-Hsin CHIU, Wei-An LAI, Meng-Hung SHEN, Wei-Cheng LIN, Jiann-Tyng TZENG, Kam-Tou SIO
  • Patent number: 11467773
    Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 11, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Yu-Chung Shen, Nien-Hung Lin
  • Patent number: 11469218
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh