Abstract: A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, each gate strip is a gate terminal of a transistor; forming a plurality of first contact vias connected to a part of the gate strips; forming a plurality of first metal strips above the plurality of gate strips; connecting one of the first metal strips to one of the first contact vias; forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, each second metal strip and one of the first metal strips are crisscrossed from top view; a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.

Abstract: An integrated circuit includes a first, second and third active region and a first, second and third conductive line. The first, second and third active regions extend in a first direction, and are on a first level of a front-side of a substrate. The second active region is between the first active region and the third active region. The first and second conductive line extend in the first direction, and are on a second level of a back-side of the substrate. The first conductive line is between the first and second active region. The second conductive line is between the second and third active region. The third conductive line extends in the second direction, is on a third level of the back-side of the substrate, overlaps the first and second conductive line, and electrically couples the first and second active regions.

Abstract: A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.

Abstract: An integrated circuit structure is disclosed, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. The gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. The first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. The first conductive line is interposed between the pair of second conductive lines in a layout view. The first feed-through via extends through the dielectric layer in a second direction different from the first direction. The first feed-through via couples the gate to the first conductive line.

Abstract: An integrated circuit includes a first power rail, a second power rail, and a power tap cell. The first power rail is at a first side of the integrated circuit. The second power rail is at a second side of the integrated circuit. The first and second sides are on opposite sides of at least a complementary field effect transistor. The power tap cell is coupled to the first power rail and the second power rail and configured to provide power from the first power rail to the second power rail.

Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Abstract: A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

Abstract: In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance.

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.

Abstract: A semiconductor device includes first, second, and third conductive regions and first and second active regions. The first conductive region has a first width and extends along a first direction. The second conductive region has a second width and extends along the first direction. The first width is greater than the second width. The first active region has a third width and extends along the first direction. The second active region has a fourth width and extends along the first direction. The third width is less than the fourth width. The third conductive region extends along a second direction and is electrically connected to the first conductive region. The second direction is different from the first direction. The first and second active regions are neighboring active regions.

Abstract: A semiconductor structure includes a plurality of cells. Each cell has a plurality of transistors, a plurality of inner metal lines, two first backside power lines and one second backside power line. The inner metal lines, the first backside power lines and the second backside power line are disposed on a back side of the transistors. The inner metal lines, the first backside power lines and the second backside power line extend along a first axis. The second backside power line is disposed between the two first backside power lines. The inner metal lines are electrically connected to the first backside power lines and the transistors, and electrically connected to the second backside power line and the transistors. The cells are arranged along a second axis, the second axis being vertical to the first axis.

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively. A length of the first conductive segment is greater than a length of the third conductive segment.

Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.

Abstract: An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.