Abstract: A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second FETs, an isolation structure, and a conductive structure. The first FET includes a first fin structure, a first array of gate structures disposed on the first fin structure, and a first array of S/D regions disposed on the first fin structure. The second FET includes a second fin structure, a second array of gate structures disposed on the second fin structure, and a second array of S/D regions disposed on the second fin structure. The isolation structure includes a fill portion and a liner portion disposed between the first and second FETs and in physical contact with the first and second arrays of gate structures. The conductive structure is disposed in the liner portion and conductively coupled to a S/D region of the second array of S/D regions.

Abstract: A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Abstract: An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

Abstract: An integrated circuit includes a first buried power rail, a second buried power rail, a first power pad in a first metal layer, and a first conductive segment beneath the first metal layer. The first buried power rail and the second buried power rail are both located beneath the first metal layer. The first power pad is configured to receive a first supply voltage through at least one first via. The first conductive segment is conductively connected to the first power pad through at least one second via between the first conductive segment and the first metal layer. The first conductive segment is conductively connected to the first buried power rail through at least one third via between the first conductive segment and the first buried power rail.

Abstract: A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) thereover corresponding to a first layer of metallization and a first layer of interconnection thereover in the semiconductor device, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing a size of the candidate pattern thereby revising the layout diagram.

Abstract: A method including depositing a first dielectric layer over a first conductive line. The method further includes forming a first opening in the first dielectric layer. The method further includes filling the first opening with a first conductive material to define a second conductive line. The method further includes depositing a second dielectric layer over the first dielectric layer. The method further includes forming a second opening in the second dielectric layer. The method further includes filling the second opening with a second conductive material to define a third conductive line. The method further includes forming a supervia opening in the first dielectric layer and the second dielectric layer. The method further includes filling the supervia opening with a third conductive material to define a supervia, wherein the supervia directly connects to the first conductive line and the third conductive line.

Abstract: A semiconductor device, including: a transistor layer, a dielectric layer, a conductive strip and a power grid structure. The transistor layer includes a first active region configured to be a source/drain terminal of a first transistor and a second active region configured to be a source/drain terminal of a second transistor. The bottom surface of the dielectric layer is in direct contact with top surfaces of the source/drain terminals of the first and second transistors. The conductive strip is included in the dielectric layer and extends from the first active region toward the second active region for signal connection. The power grid structure is arranged to direct a power source to the transistor layer from a bottom of the transistor layer.

Abstract: An integrated circuit includes a strip structure having a front side and a back side. The integrated circuit includes a gate structure on the front side of the strip structure. The integrated circuit includes an isolation structure surrounding the strip structure. The integrated circuit includes a backside via in the isolation structure. The integrated circuit includes a contact over the strip structure, wherein a first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and in contact with the backside via.

Abstract: A structure includes a first transistor of a first type, the first transistor including a first channel, a first conductive segment, and a second conductive segment, a second transistor of a second type, the second transistor including a second channel, a third conductive segment, and a fourth conductive segment, and a gate. The first channel extends through the gate between the first and second conductive segments, the second channel extends through the gate between the third and fourth conductive segments and is aligned with the first channel at a center of the first transistor, the first and third conductive segments extend away from the center of the first transistor in opposite directions, and the second and fourth conductive segments extend away from the center of the first transistor in opposite directions.

Abstract: A connector assembly includes a guiding shield cage, a receptacle connector, a partitioning bracket and a movable heat sink. The receptacle connector is provided to a rear segment of an interior of the guiding shield cage, the receptacle connector has an upper receptacle and a lower receptacle. The partitioning bracket is provided in the guiding shield cage, the partitioning bracket and the guiding shield cage together define an upper receiving space which corresponds to the upper receptacle and a lower receiving space which corresponds to the lower receptacle. The movable heat sink is assembled to the partitioning bracket, the movable heat sink is capable of moving relative to the partitioning bracket between a front position where the movable heat sink is positioned in front of a front end of the upper receptacle a front end of the lower receptacle and a rearward position where the movable heat sink at least partially enters into between the upper receptacle and the lower receptacle.

Abstract: A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, fabricating a first set of vias in a back-side of the substrate, depositing a first set of conductive structures on the back-side on a first level, depositing a second set of conductive structures on the back-side on a second level thereby forming a set of power rails, fabricating a second set of vias in the back-side, and depositing a third set of conductive structures on the back-side on a third level. The first set of vias is electrically coupled to the set of transistors. The second set of vias is electrically coupled to the first and third set of conductive structures. A first structure of the first set of conductive structures is electrically coupled to a first via of the first set of vias.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a first cell, a dielectric layer, and a snorkel structure. The first cell has an output terminal. The dielectric layer is disposed on the first cell. The snorkel structure is disposed in the dielectric layer. The snorkel structure includes a first conductive structure, a first conductive layer, and a second conductive structure. The first conductive layer is electrically connected to the output terminal of the cell. The first conductive layer is disposed on and electrically connected to the first conductive structure. The second conductive structure is disposed on and electrically connected to the first conductive layer. The second conductive structure has a topmost conductive layer buried in the dielectric layer.

Abstract: An asymmetric fused aromatic ring derivative containing sulfonyl group, which includes a structure represented by formula (I). Formula (I) is defined as in the specification. A use of the asymmetric fused aromatic ring derivative containing sulfonyl group, which is used as a photocatalyst. A hydrogen production device, which includes the asymmetric fused aromatic ring derivative containing sulfonyl group. An optoelectronic component, which includes the asymmetric fused aromatic ring derivative containing sulfonyl group.

Abstract: The present invention provides a transceiver circuit including a transmitter circuit, a frequency synthesizer and control circuit. The transmitter circuit is configured to generate a transmission signal, wherein the transmission signal is transmitted through an antenna. The frequency synthesizer is configured to generate a clock signal for the transmitter circuit to generate the transmission signal. The control circuit is configured to generate a first control signal to control the frequency synthesizer to determine a loop bandwidth of the frequency synthesizer; wherein when the transceiver circuit operates in a standby mode, the control circuit generates the first control signal to make the frequency synthesizer have a first loop bandwidth; and after a period of time after the transceiver circuit is switched from the standby mode to a transmission mode, the control circuit generates the first control signal to make the frequency synthesizer have a second loop bandwidth.

Abstract: A data protection method includes the following steps. Input data is split into a plurality of data groups. The original start-address of each data group and the data length of each data group are recorded. The data groups are reordered randomly. The reordered data groups constitute random data. The new start-address of each reordered data group is recorded. The original start-addresses, the data lengths, and the new start-addresses are collected to form a look-up table. The look-up table records the original start-addresses of the data groups and the new start-addresses of the reordered data groups. Each original start-address corresponds to one new start-address. The random data is stored in the storage memory. The look-up table is stored in the memory controller.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A method of making a semiconductor structure includes defining a first recess in an insulation layer. The method further includes forming a protection layer along a sidewall of the first recess. The method further includes forming a first conductive line in the first recess and in direct contact with the protection layer. The method further includes depositing a first insulation material over the first conductive line. The method further includes defining a second recess in the first insulation material. The method further includes forming a second conductive line in the second recess. The method further includes forming a via extending from the second conductive line, wherein the via directly contacts a sidewall of the protection layer.

Abstract: An integrated circuit includes a strip structure having a front side and a back side. A gate structure is on the front side of the strip structure. The integrated circuit includes a plurality of channel layers above the front side of the strip structure, wherein each of the plurality of channel layers is enclosed within the gate structure. An isolation structure surrounds the strip structure. The integrated circuit includes a backside via in the isolation structure. An epitaxy structure is on the front side of the strip structure. The integrated circuit includes a contact over the epitaxy structure. The contact has a first portion on a first side of the epitaxy structure. The first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and contacting the backside via.