Patents by Inventor Wei-Chieh Huang

Wei-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220216398
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Patent number: 11289646
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Publication number: 20210327748
    Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.
    Type: Application
    Filed: June 28, 2021
    Publication date: October 21, 2021
    Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
  • Publication number: 20210257548
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • Patent number: 11049767
    Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 29, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Ming Huang, Wei-Chieh Huang, Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Che Chung, Chin-Wei Liang, Ching-Sen Kuo, Jieh-Jang Chen, Feng-Jia Shiu, Sheng-Chau Chen
  • Patent number: 10998498
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • Patent number: 10958294
    Abstract: The present disclosure provides a decoding device. The decoding device includes an iteration number computing unit and a recursive decoder. The iteration number computing unit receives multiple packet parameters corresponding to a packet and computes a codeword-number-per-symbol according to packet parameters, in which the packet includes multiple symbols. The iteration number computing unit computes an iteration number according to the codeword-number-per-symbol. The recursive decoder is coupled to the iteration number computing unit, and performs a decoding operation on a codeword within a data field of the packet according to the iteration number.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 23, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Chieh Huang, Chung-Yen Liu, Yi-Syun Yang, Chung-Yao Chang
  • Patent number: 10910260
    Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Chin-Wei Liang, Feng-Jia Shiu, Hsia-Wei Chen, Jieh-Jang Chen, Ching-Sen Kuo
  • Patent number: 10826541
    Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder performs decoding operation according to a received data and an auxiliary data to obtain a target data and includes an error detection data generation circuit, a channel coding circuit, a selection circuit, and a Viterbi decoding circuit. The error detection data generation circuit performs an error detection operation on the auxiliary data to obtain an error detection data. The channel coding circuit, coupled to the error detection data generation circuit, performs channel coding on the auxiliary data and the error detection data to obtain an intermediate data. The selection circuit, coupled to the channel coding circuit, generates a to-be-decoded data according to the received data and the intermediate data. The Viterbi decoding circuit, coupled to the selection circuit, decodes the to-be-decoded data to obtain the target data.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 3, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuei-Cheng Chan, Chung-Yao Chang, Wei-Chieh Huang
  • Patent number: 10720944
    Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder and the convolutional code decoding method of the present invention perform decoding using predictive information, and therefore can demodulate/decode signals more quickly. Earlier completion of demodulation/decoding of signals can terminate the operation earlier and thereby achieve the effect of power savings. The convolutional code decoder performs decoding according to received data and auxiliary data to obtain target data, and includes a first error detection data generation circuit, a channel coding circuit, a first selection circuit, a first Viterbi decoding circuit, a second error detection data generation circuit, a comparison circuit, a second selection circuit, and a second Viterbi decoding circuit.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: July 21, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuei-Cheng Chan, Chung-Yao Chang, Wei-Chieh Huang
  • Publication number: 20200152863
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Publication number: 20200135538
    Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
  • Publication number: 20200112325
    Abstract: The present disclosure provides a decoding device. The decoding device includes an iteration number computing unit and a recursive decoder. The iteration number computing unit receives multiple packet parameters corresponding to a packet and computes a codeword-number-per-symbol according to packet parameters, in which the packet includes multiple symbols. The iteration number computing unit computes an iteration number according to the codeword-number-per-symbol. The recursive decoder is coupled to the iteration number computing unit, and performs a decoding operation on a codeword within a data field of the packet according to the iteration number.
    Type: Application
    Filed: July 23, 2019
    Publication date: April 9, 2020
    Inventors: Wei-Chieh Huang, Chung-Yen Liu, Yi-Syun Yang, Chung-Yao Chang
  • Publication number: 20200058545
    Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Wei-Chieh HUANG, Chin-Wei LIANG, Feng-Jia SHIU, Hsia-Wei CHEN, Jieh-Jang CHEN, Ching-Sen KUO
  • Publication number: 20200035918
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • Publication number: 20200028526
    Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder performs decoding operation according to a received data and an auxiliary data to obtain a target data and includes an error detection data generation circuit, a channel coding circuit, a selection circuit, and a Viterbi decoding circuit. The error detection data generation circuit performs an error detection operation on the auxiliary data to obtain an error detection data. The channel coding circuit, coupled to the error detection data generation circuit, performs channel coding on the auxiliary data and the error detection data to obtain an intermediate data. The selection circuit, coupled to the channel coding circuit, generates a to-be-decoded data according to the received data and the intermediate data. The Viterbi decoding circuit, coupled to the selection circuit, decodes the to-be-decoded data to obtain the target data.
    Type: Application
    Filed: June 17, 2019
    Publication date: January 23, 2020
    Inventors: KUEI-CHENG CHAN, CHUNG-YAO CHANG, WEI-CHIEH HUANG
  • Publication number: 20200028525
    Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder and the convolutional code decoding method of the present invention perform decoding using predictive information, and therefore can demodulate/decode signals more quickly. Earlier completion of demodulation/decoding of signals can terminate the operation earlier and thereby achieve the effect of power savings. The convolutional code decoder performs decoding according to received data and auxiliary data to obtain target data, and includes a first error detection data generation circuit, a channel coding circuit, a first selection circuit, a first Viterbi decoding circuit, a second error detection data generation circuit, a comparison circuit, a second selection circuit, and a second Viterbi decoding circuit.
    Type: Application
    Filed: June 17, 2019
    Publication date: January 23, 2020
    Inventors: KUEI-CHENG CHAN, CHUNG-YAO CHANG, WEI-CHIEH HUANG
  • Patent number: 10535815
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Patent number: 10510587
    Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Chin-Wei Liang, Feng-Jia Shiu, Hsia-Wei Chen, Jieh-Jang Chen, Ching-Sen Kuo
  • Patent number: 10461776
    Abstract: A receiving device comprises an iterative decoder, a first determination unit and a control unit. The iterative decoder is for receiving at least one coded signal and for performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration. The first determination unit is for determining whether the plurality of decoded signals diverge, to generate a first determination result. The control unit is for generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: October 29, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chuan-Hu Lin, Wei-Chieh Huang, Chia-Chun Tsui, Chung-Yao Chang