Patents by Inventor Wei-Chieh Huang

Wei-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10439135
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • Publication number: 20190140173
    Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 9, 2019
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
  • Patent number: 10270558
    Abstract: The present disclosure includes an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a search value according to a communication index and a modulation type or determine the search value according to a predetermined value, in which the communication index is related to a reception signal or a derivative thereof, the search value is associated with a search range, and a number of candidate signal value(s) in the search range is not greater than a number of all candidate signal values of the modulation type. The ML detecting circuit is configured to execute an ML calculation according to the search value and one of the reception signal and the derivative thereof, so as to calculate a log likelihood ratio of every candidate signal value in the search range.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 23, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yao Chang, Wei-Chieh Huang, Yi-Syun Yang
  • Publication number: 20190103307
    Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
    Type: Application
    Filed: February 26, 2018
    Publication date: April 4, 2019
    Inventors: Wei-Chieh HUANG, Chin-Wei LIANG, Feng-Jia SHIU, Hsia-Wei CHEN, Jieh-Jang CHEN, Ching-Sen KUO
  • Patent number: 10083914
    Abstract: An overlay mark is formed over a substrate. A plurality of first dummy features is formed outside the overlay mark in a top view. A plurality of second dummy features is formed closer to the overlay mark than the first dummy features in a top view. The first dummy features are sufficiently big to be visible to an optical machine used to scan the overlay mark. The second dummy features are sufficiently small to be invisible to the optical machine.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Wei-Chieh Huang
  • Publication number: 20180248563
    Abstract: A receiving device comprises an iterative decoder, for receiving at least one coded signal and for performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration; a first determination unit, coupled to the iterative decoder, for determining whether the plurality of decoded signals diverge, to generate a first determination result; and a control unit, coupled to the first determination unit, for generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal.
    Type: Application
    Filed: January 4, 2018
    Publication date: August 30, 2018
    Inventors: Chuan-Hu Lin, Wei-Chieh Huang, Chia-Chun Tsui, Chung-Yao Chang
  • Publication number: 20180234160
    Abstract: The present disclosure provides a demodulation method. The demodulation method includes obtaining a received signal; determining whether a multiuser interference is smaller than a threshold; performing a first signal detection operation on the received signal if the multiuser interference is smaller than the threshold, in which the first signal detection operation detects a single layer of spatial data in the received signal; and performing a second signal detection operation on the received signal if the multiuser interference is greater than the threshold, in which the second signal detection operation detects multiple layers of spatial data in the received signal.
    Type: Application
    Filed: August 28, 2017
    Publication date: August 16, 2018
    Inventors: Chung-Yao Chang, Wei-Chieh Huang, Yi-Syun Yang
  • Patent number: 10007507
    Abstract: In a method for updating firmware of a battery included in a rechargeable battery module of a portable electronic device, the portable electronic device stores a booting instruction set of the firmware in a battery monitoring unit of the rechargeable battery module, and stores a basic input/output system (BIOS) of the portable electronic device in a non-volatile memory disposed externally of the rechargeable battery module. In response to BIOS update information that includes an updated main instruction set of the firmware, the portable electronic device updates the BIOS, including the main instruction set of the firmware using the BIOS update information.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: June 26, 2018
    Assignee: Wistron Corporation
    Inventor: Wei Chieh Huang
  • Patent number: 10007446
    Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: June 26, 2018
    Assignee: Macronix International Co., Ltd.
    Inventors: Wei-Chieh Huang, Li-Chun Huang, Yu-Ming Chang, Hung-Sheng Chang, Hsiang-Pang Li, Ting-Yu Liu, Chien-Hsin Liu, Nai-Ping Kuo
  • Publication number: 20180108835
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 19, 2018
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Patent number: 9847477
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Patent number: 9817588
    Abstract: A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: November 14, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Ming Chang, Wei-Chieh Huang, Li-Chun Huang, Hung-Sheng Chang, Hsiang-Pang Li, Ting-Yu Liu, Chien-Hsin Liu, Nai-Ping Kuo
  • Publication number: 20170317786
    Abstract: The present disclosure includes an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a search value according to a communication index and a modulation type or determine the search value according to a predetermined value, in which the communication index is related to a reception signal or a derivative thereof, the search value is associated with a search range, and a number of candidate signal value(s) in the search range is not greater than a number of all candidate signal values of the modulation type. The ML detecting circuit is configured to execute an ML calculation according to the search value and one of the reception signal and the derivative thereof, so as to calculate a log likelihood ratio of every candidate signal value in the search range.
    Type: Application
    Filed: March 21, 2017
    Publication date: November 2, 2017
    Inventors: CHUNG-YAO CHANG, WEI-CHIEH HUANG, YI-SYUN YANG
  • Publication number: 20170294576
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Wei-Chieh Huang, Jieh-Jang Chen
  • Patent number: 9783881
    Abstract: A linear evaporation apparatus includes a thermal insulation chamber, and crucibles, evaporation material heaters and a mixing chamber installed in the thermal insulation chamber. The mixing chamber includes a flow limiting and adjusting layer, a flow channel adjusting member, a mixed layer and a linear evaporation layer. The flow limiting and adjusting layer is a rectangular sheet with flow limit holes corresponsive to the crucibles respectively; the flow channel adjusting member is an interconnected structure having at least one flow inlet corresponsive to some of the flow limit holes and at least one flow outlet, and the mixed layer is a substantially I-shaped sheet structure, and the linear evaporation layer is a rectangular sheet having a linear source evaporation opening tapered from both ends to the middle, so as to improve the uniformity of the thin film and the utilization of the evaporation materials.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: October 10, 2017
    Assignee: NATIONAL CHUNG-SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Shih-Chang Liang, Wei-Chieh Huang, Chao-Nan Wei, Cuo-Yo Ni, Hui-Yun Bor
  • Patent number: 9760478
    Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: September 12, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Chang, Tai-Chun Kuo, Wei-Chieh Huang, Ping-Hsien Lin, Tzu-Hsiang Su
  • Patent number: 9574264
    Abstract: In a method for evaporation depositing uniform thin films, a film is deposited on a substrate of a vacuum environment while maintaining a constant deposition rate. A cover is installed on a wall of the evaporation vessel. When the evaporation material is heated to an evaporation state and the interior of the evaporation vessel reaches a first vapor saturation pressure, the vapor of the evaporation material flows towards a pressure stabilizing chamber. When the pressure stabilizing chamber reaches a second vapor saturation pressure which is smaller than the first vapor saturation pressure, the vacuum environment has a vacuum background pressure which is smaller than the second vapor saturation pressure, so that the evaporation material vapor flows from the pressure stabilizing chamber towards the vacuum environment at constant rate due to the pressure difference, so as to evaporate the substrate.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: February 21, 2017
    Assignee: NATIONAL CHUNG-SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Shih-Chang Liang, Wei-Chieh Huang, Chao-Nan Wei, Cuo-Yo Ni, Hui-Yun Bor
  • Publication number: 20170047291
    Abstract: An overlay mark is formed over a substrate. A plurality of first dummy features is formed outside the overlay mark in a top view. A plurality of second dummy features is formed closer to the overlay mark than the first dummy features in a top view. The first dummy features are sufficiently big to be visible to an optical machine used to scan the overlay mark. The second dummy features are sufficiently small to be invisible to the optical machine.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventor: Wei-Chieh Huang
  • Publication number: 20160328161
    Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.
    Type: Application
    Filed: May 5, 2015
    Publication date: November 10, 2016
    Inventors: Wei-Chieh HUANG, Li-Chun HUANG, Yu-Ming CHANG, Hung-Sheng CHANG, Hsiang-Pang LI, Ting-Yu LIU, Chien-Hsin LIU, Nai-Ping KUO
  • Patent number: 9484310
    Abstract: A plurality of first miniature elements of an overlay mark is formed in a first layer. A plurality of second miniature elements of the overlay mark is formed in a second layer different from the first layer. A plurality of dummy features is formed around the overlay mark. The dummy features are formed such that they each have a dimension below a resolution of an alignment detection tool configured to optically scan the overlay mark in an alignment process.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Wei-Chieh Huang