Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

Abstract: A method for performing a lithographic process over a semiconductor wafer is provided. The method includes coating a photoresist layer over a material layer which is formed on the semiconductor wafer in a track apparatus. The method further includes transferring the semiconductor wafer from the track apparatus to an exposure apparatus. The method also includes measuring a height of the photoresist layer before the removal of the semiconductor wafer from the track apparatus. In addition, the method includes measuring height of the material layer in the exposure apparatus. The method also includes determining a focal length for exposing the semiconductor wafer according to the height of the photoresist layer and the height of the material layer.

Abstract: The present inventors have conceived of a multi-stage process gas delivery system for use in a substrate processing apparatus. In certain implementations, a first process gas may first be delivered to a substrate in a substrate processing chamber. A second process gas may be delivered, at a later time, to the substrate to aid in the even dosing of the substrate. Delivery of the first process gas and the second process gas may cease at the same time or may cease at separate times.

Abstract: A method for fabricating a solar cell is provided and has steps of: providing a transparent conductive substrate; forming a porous supporting layer on the transparent conductive substrate; forming a porous conductive counter electrode layer on the porous supporting layer, where the porous conductive counter electrode layer includes a carrier blocking layer and a conductive layer, and the carrier blocking layer is between the porous supporting layer and the conductive layer; and providing a light-absorbing material penetrating from the porous conductive counter electrode layer. The light-absorbing material fills within the porous supporting layer through a plurality of pores in the porous conductive counter electrode layer.

Abstract: The present inventors have conceived of a multi-stage process gas delivery system for use in a substrate processing apparatus. In certain implementations, a first process gas may first be delivered to a substrate in a substrate processing chamber. A second process gas may be delivered, at a later time, to the substrate to aid in the even dosing of the substrate. Delivery of the first process gas and the second process gas may cease at the same time or may cease at separate times.

Abstract: Systems and methods for monitoring the focus of an EUV lithography system are disclosed. Another aspect includes a method having operations of measuring a first shift value for a first patterned set of sub-structures of a focus test structure on a wafer and measuring a second shift value for a second patterned set of sub-structures of the test structure on the wafer. The test structure may be formed on the wafer using asymmetric illumination, with the first patterned set of sub-structures having a first pitch and the second patterned set of sub-structures having a second pitch that is different from the first pitch. The method may further include determining a focus shift compensation for an illumination system based on a difference between the first shift value and the second shift value.

Abstract: A perovskite solar cell is provided with a perovskite material layer having a first surface and a second surface opposite to the first surface; an electron transport layer disposed on the first surface; and a gold-nickel oxide layer disposed on the second surface. Furthermore, a manufacturing method of the perovskite solar cell is disclosed with steps of providing a transparent substrate; forming a gold-nickel oxide layer on the transparent substrate; and forming a perovskite material layer on the gold-nickel oxide layer.

Abstract: Systems and methods for monitoring the focus of an EUV lithography system are disclosed. Another aspect includes a method having operations of measuring a first shift value for a first patterned set of sub-structures of a focus test structure on a wafer and measuring a second shift value for a second patterned set of sub-structures of the test structure on the wafer. The test structure may be formed on the wafer using asymmetric illumination, with the first patterned set of sub-structures having a first pitch and the second patterned set of sub-structures having a second pitch that is different from the first pitch. The method may further include determining a focus shift compensation for an illumination system based on a difference between the first shift value and the second shift value.

Abstract: A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.

Abstract: The present inventors have conceived of a multi-stage process gas delivery system for use in a substrate processing apparatus. In certain implementations, a first process gas may first be delivered to a substrate in a substrate processing chamber. A second process gas may be delivered, at a later time, to the substrate to aid in the even dosing of the substrate. Delivery of the first process gas and the second process gas may cease at the same time or may cease at separate times.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI) structure, and a shielding layer. The semiconductor substrate has electrical circuitry. The dielectric layer is formed on the semiconductor substrate. The passivation layer is formed on the dielectric layer. The first protective layer is formed on the passivation layer. The PPI structure is disposed on the first protective layer and has a signal line and a ground line. The shielding layer is disposed over the semiconductor substrate and between the signal line and the electrical circuitry. The shielding layer is substantially equi-potentially connected to the ground line of the PPI structure.

Abstract: A power control device for an electronic device includes a power switching unit for switching to output a dc power source to a load of the electronic device according to a power switching signal, a switching detection unit for responding a power switching status to generate a switching detection signal, a status latch module for generating the power switching signal according to the switching detection signal, a first status signal and a second status signal, and a logic unit for generating the first status signal and the second status signal for the status latch module according to the power switching signal, such that the status latch module latches the first status signal and the second status signal.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI) structure, and a shielding layer. The semiconductor substrate has electrical circuitry. The dielectric layer is formed on the semiconductor substrate. The passivation layer is formed on the dielectric layer. The first protective layer is formed on the passivation layer. The PPI structure is disposed on the first protective layer and has a signal line and a ground line. The shielding layer is disposed over the semiconductor substrate and between the signal line and the electrical circuitry. The shielding layer is substantially equi-potentially connected to the ground line of the PPI structure.

Abstract: An integrated circuit (IC) package includes an IC chip, a package carrier, and a plurality of conductive bumps connecting the IC chip to the package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The active surface has a core area and a signal area surrounding the core area. The IC layered structure includes a first physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The first inner pads are arranged in multiple rows in the signal area.

Abstract: A fastening module for fastening a data storage device is provided. The data storage device includes first and second positioning apertures. A frame of the fastening module includes a retaining hole, and first and second positioning holes. The data storage device is slidably received in the frame. A securing member of the fastening module includes a main body, a pivot member, and a pin. The main body includes a pivot hole pivotally connected by the pivot member. A securing piece of the pivot member passes through the retaining hole and rotates relative to the main body to fasten the securing member to the frame. When the securing piece passes through the retaining hole, the pin passes through either the first or second positioning hole and inserts into either the first or second positioning aperture to fasten the data storage device at different positions.

Abstract: A stacked semiconductor device and an associated manufacturing method are disclosed. A first semiconductor unit having a first surface, which is defined as being not a polar plane, is provided. At least one pit is formed on the first surface, and the pit has a second surface that lies at an angle relative to the first surface. A polarization enhanced tunnel junction is formed on the second surface, and a second semiconductor unit is formed above the tunnel junction.

Abstract: A fastening module for fastening a data storage device is provided. A fastening trough is formed at a lower surface of the data storage device. The fastening module includes a frame bracket, a fastening member, and a buckling member. The frame bracket is used for carrying the data storage device. The frame bracket includes a lower frame and two side frames. The side frames are connected to two sides of the lower frame. The lower frame includes a clamping hole. The fastening member is disposed at the clamping hole and inserted into a fastening trough, so as to prevent the data storage device from moving. The buckling member is movably disposed at the side frames to buckle an upper surface of the data storage device.

Abstract: An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.

Abstract: A stacked semiconductor device and an associated manufacturing method are disclosed. A first semiconductor unit having a first surface, which is defined as being not a polar plane, is provided. At least one pit is formed on the first surface, and the pit has a second surface that lies at an angle relative to the first surface. A polarization enhanced tunnel junction is formed on the second surface, and a second semiconductor unit is formed above the tunnel junction.

Abstract: A light-emitting diode (LED) device includes a first LED, a second LED, and a superlattice structure by which the first and the second LEDs are stacked. The superlattice structure has an absorption spectra, the first active layer of the first LED has a first emission spectra, and the second active layer of the second LED has a second emission spectra. The absorption spectra is located on a shorter-wavelength side of at least one of the first and the second emission spectra.