Abstract: An embedded-damper speaker for an information handling system includes a top speaker housing, a bottom speaker housing, and a damper. The bottom speaker housing is in physical communication with the top speaker housing. The damper is secured in between the top and bottom speaker housings. The damper reduces acoustic resonance between the embedded-damper speaker and the information handling system.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: A data processing method for the machine learning and an electronic device using the same are provided. The data processing method for the machine learning includes the following steps. For a plurality of sources, a source balancing procedure is performed on an original measuring data to obtain a balanced distribution map. For each of the subjects, a personalization scaling procedure is performed on a plurality of detection values to obtain a personalized scaled measuring data. For each of the sources, a source scaling procedure is performed on the detection values to obtain a by-source scaled measuring data. The balanced distribution map, the personalized scaled measuring data and the by-source scaled measuring data are combined to obtain a balanced personalized scaled data and a balanced by-source scaled data. Based on the balanced personalized scaled data and the balanced by-source scaled data, some of the detection items are outputted.

Abstract: This disclosure describes a network management system configured to determine, for each AP of the plurality of APs and based on received signal strength indicators (RSSIs) of each AP of the plurality of APs, one or more strong neighbors of each AP. compute an AP redundancy score for each AP of the plurality of APs indicative of a redundancy of each AP; compute, based on the AP redundancy scores, at least one of: a switch redundancy score for each network switch associated with one or more of the plurality of APs, wherein the switch redundancy score is indicative of a redundancy of each network switch, or a site redundancy score, wherein the site redundancy score is indicative of an overall redundancy of the network site; and invoke, based on the AP redundancy scores, the switch redundancy score, or the site redundancy score, one or more actions.

Abstract: The present invention provides a vessel navigation boundary collision avoidance method. Specifically, the vessel navigation boundary collision avoidance method first performs step (A) of providing at least one boundary. In step (B), a plurality of dummy ships are established along the at least one boundary, wherein the dummy ships are freezing and each of the dummy ships is connected to at least a part of another via an intersection point. In step (C), a dummy ship domain and a dummy obstacle domain are sequentially formed according to each of the dummy ships and each of the intersection points. In step (D), a dummy ship anti-collision circle and a dummy obstacle anti-collision circle are sequentially generated based on the dummy ship domain and the dummy obstacle domain if a sailing ship domain is to have a possibility of invading the dummy ship domain and the dummy obstacle domain.

Abstract: A semiconductor structure includes a substrate, a first silicide, and a second silicide. The substrate has a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type. The first silicide is on the first epitaxy region, the first silicide comprising a first metal and a second metal, and the second silicide is on the second epitaxy region. A work function of the first silicide is greater than a work function of the second silicide.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a first resistance-capacitance (RC) timer circuit, a second RC timer circuit, a voltage pull-down circuit, a voltage pull-up circuit, a discharge circuit, and a discharge control circuit. The first RC timer circuit is coupled between a first power supply voltage and a reference voltage. The second RC timer circuit is coupled between a second power supply voltage and the reference voltage. The voltage pull-up circuit is coupled between the second power supply voltage and the reference voltage through a first resistor. The discharge circuit is coupled between the second power supply voltage and the reference voltage. The discharge control circuit is coupled between a third node and the reference voltage, and controls the discharge circuit using a first voltage generated by the first RC timer circuit.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.

Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Abstract: A circuit module with improved timing control, may comprise a functional circuit, a control circuit, a main auxiliary circuit and an additional auxiliary circuit. The control circuit may control operation timing of the functional circuit according to response characteristics of a first node. When enabled, the main auxiliary circuit may provide main conduction path(s) between the first node and a base node. Respectively when enabled and disabled, the additional auxiliary circuit may provide and not provide additional conduction path(s) between the first node and the base node. When the control circuit controls the operation timing of the functional circuit, the main auxiliary circuit may be enabled, and the additional auxiliary circuit may be disabled or enabled according to whether a mode signal is of a first mode level or a second level.

Abstract: The present invention relates to a joint automatic audio visual driven facial animation system that in some example embodiments includes a full scale state of the art Large Vocabulary Continuous Speech Recognition (LVCSR) with a strong language model for speech recognition and obtained phoneme alignment from the word lattice.

Abstract: A thermal exchange device including a sliding plate and a thermal exchange unit is provided. The sliding plate includes a plate-shaped body, a first flange and a second flange. The first flange, protruding from a first side of the plate-shaped body, has a guide slit including a first section, a second section and a guide slit connecting the two sections. The first section, extending in a direction parallel to a long axis of the plate-shaped body, is separated from the first side by a first distance. The second section, extending to the said direction, is separated from the first side by a second distance greater than the first distance. The second flange, protruding from a second side of the plate-shaped body, defines a slide groove with the first flange and the plate-shaped body. The thermal exchange unit, at least partly received in the slide groove, includes a guide rod.

Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Abstract: An information handling system housing includes an interior frame that integrates removeable slot adapters and a garage to hold the slot adapters once separate from the frame. In one example embodiment, a slot adapter has plural support structures and screw openings with an offset bottom surface alignment pin so that insertion into openings in different device slots will support different types of devices, such as solid state drives (SSDs) and wireless network interface controllers.

Abstract: An information handling system housing includes an interior frame that integrates removeable slot adapters and a garage to hold the slot adapters once separate from the frame. In one example embodiment, a slot adapter has plural support structures and screw openings with an offset bottom surface alignment pin so that insertion into openings in different device slots will support different types of devices, such as solid state drives (SSDs) and wireless network interface controllers.

Abstract: Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.