Patents by Inventor Wei Chu

Wei Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12182919
    Abstract: The present invention relates to a joint automatic audio visual driven facial animation system that in some example embodiments includes a full scale state of the art Large Vocabulary Continuous Speech Recognition (LVCSR) with a strong language model for speech recognition and obtained phoneme alignment from the word lattice.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: December 31, 2024
    Assignee: Snap Inc.
    Inventors: Chen Cao, Xin Chen, Wei Chu, Zehao Xue
  • Publication number: 20240402404
    Abstract: An infrared filter film layer and an infrared filter structure are provided. The infrared filter film layer includes at least one silicon-based layer, at least one isolation layer, and at least one oxide layer that are stacked with each other. The at least one isolation layer is disposed between the at least one silicon-based layer and the at least one oxide layer. Through this configuration, the infrared filter film layer has good quality, such that an amount of wavelength drift is small in application. The infrared filter structure includes a light-transmitting substrate and the infrared filter film layer.
    Type: Application
    Filed: May 28, 2024
    Publication date: December 5, 2024
    Inventors: CHIH-FENG WANG, KUO-YIN HUANG, WEN-YU WANG, Ke-Peng Chang, YUNG-PENG CHANG, Cheng-Wei Chu
  • Publication number: 20240405012
    Abstract: An electrostatic discharge (ESD) protection cell region (of a semiconductor device) includes a resistor-diode ladder and a power clamp circuit coupled in parallel between a first power rail PR1 and a second power rail PR2. The resistor-diode ladder is also coupled between an input/output (I/O) pad of the semiconductor device and core circuitry of the semiconductor device. The resistor-diode ladder includes: a first diode coupled between a first node and the first power rail; a first resistor coupled between the first node and a second node; a second diode coupled between the second node and the first power rail; a third diode coupled between the first node and the second power rail; and a fourth diode coupled between the second node and the second power rail. The first node is coupled to the I/O pad. The resistor-diode ladder is coupled between the I/O pad and the core circuitry.
    Type: Application
    Filed: November 9, 2023
    Publication date: December 5, 2024
    Inventors: Li-Wei ChU, Jam-Wem LEE, Wun-Jie LIN, Shou Ming LIU
  • Publication number: 20240387507
    Abstract: A method of making a semiconductor device includes manufacturing lines extending in a first direction over doped zones in a substrate, wherein each of the lines has a line width measured along a first direction. The method further includes trimming the lines into line segments having ends over an isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the first direction, and the line width is substantially similar to the gate electrode width.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Li-Wei CHU, Wun-Jie LIN, Yu-Ti SU, Ming-Fu TSAI, Jam-Wem LEE
  • Publication number: 20240379759
    Abstract: A semiconductor device includes a first transistor, a second transistor, a first metal silicide layer, a second metal silicide layer, and an isolation structure. The first transistor includes a first channel layer, a first gate structure, and first source/drain epitaxy structures. The second transistor includes a second channel layer, a second gate structure, and second source/drain epitaxy structures. The first metal silicide layer is over one of the first source/drain epitaxy structures. The second metal silicide layer is over one of the second source/drain epitaxy structures. The isolation structure covers the one of the first source/drain epitaxy structures and the one of the second source/drain epitaxy structures, wherein in a cross-sectional view, the one of the first source/drain epitaxy structures is separated from the isolation structure through the first metal silicide layer, while the one of the second source/drain epitaxy structures is in contact with the isolation structure.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yip LOH, Li-Wei CHU, Hong-Mao LEE, Hung-Chang HSU, Hung-Hsu CHEN, Harry CHIEN, Chih-Wei CHANG
  • Publication number: 20240379457
    Abstract: A semiconductor structure includes a substrate, a first silicide, and a second silicide. The substrate has a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type. The first silicide is on the first epitaxy region, the first silicide comprising a first metal and a second metal, and the second silicide is on the second epitaxy region. A work function of the first silicide is greater than a work function of the second silicide.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: SUNG-LI WANG, PENG-WEI CHU, YASUTOSHI OKUNO
  • Publication number: 20240357281
    Abstract: An embedded-damper speaker for an information handling system includes a top speaker housing, a bottom speaker housing, and a damper. The bottom speaker housing is in physical communication with the top speaker housing. The damper is secured in between the top and bottom speaker housings. The damper reduces acoustic resonance between the embedded-damper speaker and the information handling system.
    Type: Application
    Filed: April 19, 2023
    Publication date: October 24, 2024
    Inventors: Jing-Tang Wu, Bo-Wei Chu
  • Publication number: 20240347531
    Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Lin PENG, Han-Jen YANG, Jam-Wem LEE, Li-Wei CHU
  • Patent number: 12100702
    Abstract: A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wei Chu, Wun-Jie Lin, Yu-Ti Su, Ming-Fu Tsai, Jam-Wem Lee
  • Publication number: 20240307007
    Abstract: An alarm system an alarm method for a medical emergency are provided. The alarm method includes: obtaining a physiological signal of a user by a sensor of a portable electronic device; receiving the physiological signal from the portable electronic device, determining whether an abnormal event has occurred according to the physiological signal, and transmitting first feedback information corresponding to the physiological signal to a server in response to the abnormal event by the terminal device; and outputting an alarm message according to the first feedback information by the server.
    Type: Application
    Filed: November 21, 2023
    Publication date: September 19, 2024
    Applicants: Acer Incorporated, Far Eastern Memorial Hospital
    Inventors: Sheng-Wei Chu, Tsung-Hsien Tsai, Ke-Han Pan, Yueh-Yarng Tsai, Pei-Jung Chen, Jun-Hong Chen, Yen-Wen Wu, Jen-Tang Sun
  • Publication number: 20240304499
    Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Inventors: Peng-Wei Chu, Sung-Li Wang, Yasutoshi Okuno
  • Patent number: 12080368
    Abstract: A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: September 3, 2024
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Nan-Chun Lien, Li-Wei Chu, Ting-Wei Chang
  • Publication number: 20240289565
    Abstract: An information handling system has a SIM card slot that accepts a micro SIM card and also accepts a nano SIM card when inserted in an adapter having an outer perimeter of a micro SIM card. The adapter holds contact pads of the nano SIM card in alignment with spring contacts of SIM card socket. When the adapter is inserted into the SIM card socket without a nano SIM card, a contact cover coupled to an eject member has an opening through which spring contacts extend against contact pads, and when the eject member is pressed inward to eject the SIM card adapter, the contact cover moves inward to press down on the spring contacts so that the SIM card adapter is kept clear of the spring contact through ejection.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Applicant: Dell Products L.P.
    Inventors: Chia-Ting Hu, Chun-Po Chen, Bo-Wei Chu
  • Publication number: 20240289647
    Abstract: A knowledge graph processing method is provided. The method includes: selecting several nodes and their edges from a shared knowledge graph based on one or more entity types involved in a target service domain, to obtain a target subgraph, where the shared knowledge graph is obtained by fusing knowledge graphs of one or more service domains; processing the target subgraph to extract one or more graph features, where the graph feature includes some or all of the following: a node representation vector, an edge representation vector, a graph structure feature, a semantic feature of graph text information, and a graph rule feature; and providing the graph feature to a target data processing task of the target service domain, where the graph feature is used to serve as an input feature of the target data processing task together with a task customization feature.
    Type: Application
    Filed: October 17, 2022
    Publication date: August 29, 2024
    Inventors: Deng ZHAO, Jianshan HE, Bin HU, Tao FANG, Zhizhen LIU, Zhengke GUI, Lei LIANG, Taifeng WANG, Wei CHU
  • Patent number: 12074110
    Abstract: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
  • Patent number: 12051691
    Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Lin Peng, Han-Jen Yang, Jam-Wem Lee, Li-Wei Chu
  • Patent number: 12051896
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Patent number: 12047854
    Abstract: A bluetooth communication method includes: a first communication device establishing bluetooth connection with a second communication device, wherein the first communication device is configured to execute multiple tasks; the first communication device communicating with the second communication device through the bluetooth connection, to allocate at least one task of the multiple tasks to the second communication device for execution; and the first communication device receiving an execution result of the at least one task from the second communication device through the bluetooth connection.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: July 23, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Wei-Chu Lai, Wei-Lun Wan, Fei Kong
  • Publication number: 20240222363
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Li-Wei CHU, Ming-Fu TSAI, Jam-Wem LEE, Yu-Ti SU
  • Patent number: 12026019
    Abstract: A portable information handling system having a portable housing with first and second housing portions rotationally coupled by a hinge having an adjustable torque and a sensor disposed at a front corner of a housing portion reduces torque provided by the hinge when in a closed position and an indication is sensed of an end user opening the housing portions. Reducing torque of the hinge that resists housing rotation from the closed position aids an end user in a single handed rotation of the housing to an open position by allowing the weight of the housing to be sufficient to hold the housing in place on a support surface while the housing rotates open.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: July 2, 2024
    Assignee: Dell Products L.P.
    Inventors: Kuan-Hua Chiou, Chunpo Chen, Wen-Hsing Lin, Chia-Ting Hu, Yu-Chun Hsieh, Bo-Wei Chu, Jou-Yen Lu