Patents by Inventor Wei Chung Wang

Wei Chung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100044722
    Abstract: A sensing module comprises a carrier, a sensor, a substrate, and a plurality of chips. The carrier has a carrying surface and a back surface opposite to the carrying surface. The sensor and the substrate are disposed on the carrying surface and are electrically connected to the carrier respectively. The chips are disposed on the substrate and are electrically connected to the substrate respectively. The production cost of the sensing module is low.
    Type: Application
    Filed: November 28, 2008
    Publication date: February 25, 2010
    Inventors: Hung-Ching LAI, Kuo-Hsiung Li, Hui-Hsuan Chen, Wei-Chung Wang
  • Publication number: 20100000775
    Abstract: A circuit substrate suitable for being connected to at least one solder ball is provided. The circuit substrate includes a substrate, at least one bonding pad, and a solder mask. The substrate has a surface. The bonding pad is disposed on the surface of the substrate for being connected to the solder ball. The solder mask covers the surface of the substrate and has an opening for exposing a portion of the bonding pad. The opening has a first end and a second end. As compared with the second end, the first end is much farther from the bonding pad, and a diameter of the first end is larger than that of the second end.
    Type: Application
    Filed: June 23, 2009
    Publication date: January 7, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: CHI-CHIH SHEN, Jen-Chuan Chen, Wei-Chung Wang
  • Patent number: 7642132
    Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: January 5, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
  • Publication number: 20090127648
    Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a first deposition step to fill a first dielectric material into the opening using a first deposition method. The first deposition method has a bottom deposition rate substantially greater than a sidewall deposition rate. The method further includes isotropically etching the first dielectric material, wherein at least a bottom portion of the first dielectric material remains after the etching; and performing a second deposition step to fill a remaining portion of the opening with a second dielectric material. The first deposition method may be a high-density plasma chemical vapor deposition. The second deposition method may be a high-aspect ratio process.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 21, 2009
    Inventors: Neng-Kuo Chen, Chih-Hsiang Chang, Cheng-Yuan Tsai, Wei-Chung Wang, Chun-Te Li
  • Patent number: 7528053
    Abstract: A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: May 5, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
  • Publication number: 20090091015
    Abstract: A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks.
    Type: Application
    Filed: September 24, 2008
    Publication date: April 9, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Chih Shen, Cheng-Yin Lee, Wei-Chung Wang
  • Patent number: 7501342
    Abstract: A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 10, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei Chung Wang, Po Jen Cheng, Hsueh An Yang, Pei Chun Chen
  • Publication number: 20090046436
    Abstract: A MEMS package includes a first board, a second board and a laminate material. The first board includes a lower metallic trace, a metallic diaphragm and a through opening. The lower metallic trace is located on the lower surface of the first board, and the metallic diaphragm is disposed on the lower metallic trace. The second board includes an upper metallic trace and a metallic electrode. The upper metallic trace is located on the upper surface of the second board, the metallic electrode is disposed on the upper metallic trace, and the metallic electrode is corresponding to the metallic diaphragm. The laminate material is disposed between the lower and upper metallic traces, and includes a hollow portion for accommodating the metallic electrode and metallic diaphragm, wherein a sensing unit is formed by the metallic electrode, the hollow portion and the metallic diaphragm, and is corresponding to the through opening.
    Type: Application
    Filed: May 23, 2008
    Publication date: February 19, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING
    Inventors: Hsueh An YANG, Meng Jen WANG, Wei Chung WANG, Ming Chiang LEE, Wei Pin HUANG, Feng Chen CHENG
  • Patent number: 7491568
    Abstract: The present invention relates to a wafer level package and method for making the same. The method of the invention comprises: (a) providing a metal layer, the metal layer having a first surface and a second surface; (b) forming a plurality of first caves and a plurality of second caves on the first surface; (c) forming a cover in each first cave and around each first cave and forming a conductive portion in each second cave and around each second cave; (d) disposing a wafer onto the covers and the conductive portions; and (e) removing the metal layer. Whereby the process of the invention will be shortened and the cost will decrease. The method of invention provides the conductive portions used for convenient leads connecting with outer components and further decreases the size of the package.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: February 17, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Chung Wang
  • Publication number: 20090039526
    Abstract: The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 12, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Meng-Jen Wang, Wei-Chung Wang
  • Publication number: 20080303167
    Abstract: A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar.
    Type: Application
    Filed: March 18, 2008
    Publication date: December 11, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei Chung WANG, Po Jen CHENG, Hsueh An YANG, Pei Chun CHEN
  • Publication number: 20080272486
    Abstract: A chip package structure includes a carrier, an interposer, a plurality of electrically conductive elements, a first sealant, a chip, and a second sealant. The interposer is disposed on the carrier. The electrically conductive elements electrically connect the interposer and the carrier. The first sealant seals the electrically conductive elements. A plurality of bumps of the chip is connected to the interposer. The second sealant seals the bumps. A first glass transition temperature of the first sealant is higher than a second glass transition temperature of the second sealant. Since glass transition temperatures of the first sealant and the second sealant are different, and the first glass transition temperature of the first sealant is higher than the second glass transition temperature of the second sealant, the inner stress will be lowered and the yield is promoted.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 6, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chung Wang, Meng-Jen Wang, Tong-Hong Wang
  • Patent number: 7446404
    Abstract: A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: November 4, 2008
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
  • Patent number: 7410886
    Abstract: A method of fabricating protective caps for protecting devices on wafer surface includes: (a) providing a non-metal cap substrate and forming a metal layer on the non-metal cap substrate; (b) forming a plurality of cavities on a surface of the metal layer, wherein the location of each cavity corresponds to each of the devices on the wafer surface; and (c) forming a protective cap in each cavity and forming a plurality of bonding media around the cavities.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: August 12, 2008
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Chung Wang
  • Patent number: 7336259
    Abstract: An input device has a body and a battery that is retained in the body. A receiver is coupled to a computer via a cable, with the body removably engaging the receiver. The computer delivers power through the cable and the receiver to charge the battery, while the input device simultaneously transmits operational signals to the receiver for further transmission to the computer.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: February 26, 2008
    Assignee: KYE Systems Corp.
    Inventors: Tsu-Nan Li, Wei-Chung Wang, Yu-Wen Tseng
  • Patent number: 7287863
    Abstract: A light tunnel with a gradient filter layer includes a light tunnel body and a gradient filter layer. In this case, the gradient filter layer is disposed at a light emerging side. The transmission rate at the central area of the gradient filter layer is smaller than the transmission rate at the edge area of the gradient filter layer.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: October 30, 2007
    Assignee: Prodisc Technology Inc.
    Inventors: Nai-Yueh Liang, Shu-Ching Chan, Wei-Chung Wang, Chong-Han Tsai, Ta-Kun Kung, Yen-Chun Chou
  • Publication number: 20070205499
    Abstract: The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.
    Type: Application
    Filed: December 27, 2006
    Publication date: September 6, 2007
    Inventors: Wei-Chung Wang, Sung-Mao Wu, Hsueh-An Yang, Kuo-Pin Yang, Chian-Chi Lin
  • Publication number: 20070172984
    Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 26, 2007
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
  • Publication number: 20070172985
    Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a metal; (g) removing the dry film, and patterning the conductive layer; (h) removing a part of the metal in the blind hole to form a space; (i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal; (k) stacking a plurality of the wafers, and performing a reflow process; and (l) cutting the stacked wafers, so as to form a plurality of three-dimensional packages.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 26, 2007
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chain-Chi Lin
  • Publication number: 20070172986
    Abstract: The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package structure comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first metal, a first solder, a second wafer, at least one second hole, a second isolation layer, a second conductive layer, a second metal and a second space. The first wafer has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The lower end of the first conductive layer extends below the surface of the first wafer. The first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 26, 2007
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin