Patents by Inventor Wei-Ding Wu

Wei-Ding Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11305980
    Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Chun Weng, Lavanya Sanagavarapu, Ching-Hsiang Hu, Wei-Ding Wu, Shyh-Wei Cheng, Ji-Hong Chiang, Hsin-Yu Chen, Hsi-Cheng Hsu
  • Publication number: 20210116713
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Inventors: Hsin-Yu CHEN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Yen-Chiang LIU, Jiun-Jie CHIOU, Li-Yang TU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Hsi-Cheng HSU
  • Publication number: 20210116714
    Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, and wherein the conductive layer is formed over at least one of the following: the first surface of the first dielectric layer and a portion of sidewalls of each of the plurality of via holes, and wherein the conductive layer is configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Inventors: Hsin-Yu CHEN, Yen-Chiang LIU, Jiun-Jie CHIOU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Hsi-Cheng HSU
  • Publication number: 20200387686
    Abstract: Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.
    Type: Application
    Filed: May 7, 2020
    Publication date: December 10, 2020
    Inventors: You-Cheng JHANG, Han-Zong PAN, Wei-Ding WU, Jiu-Chun WENG, Hsin-Yu CHEN, Chen-San CHOU, Chin-Min LIN
  • Publication number: 20200123003
    Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Jui-Chun Weng, Lavanya Sanagavarapu, Ching-Hsiang Hu, Wei-Ding Wu, Shyh-Wei Cheng, Ji-Hong Chiang, Hsin-Yu Chen, Hsi-Cheng Hsu
  • Patent number: 10532925
    Abstract: The present disclosure relates to a micro-electromechanical system (MEMs) package. In some embodiments, the MEMs package has a plurality of conductive interconnect layers disposed within a dielectric structure over an upper surface of a first substrate. A heating element is electrically coupled to a semiconductor device within the first substrate by one or more of the plurality of conductive interconnect layers. The heating element is vertically separated from the first substrate by the dielectric structure. A MEMs substrate is coupled to the first substrate and has a MEMs device. A hermetically sealed chamber surrounding the MEMs device is disposed between the first substrate and the MEMs substrate. An out-gassing material is disposed laterally between the hermetically sealed chamber and the heating element.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
  • Patent number: 10513432
    Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Chun Weng, Lavanya Sanagavarapu, Ching-Hsiang Hu, Wei-Ding Wu, Shyh-Wei Cheng, Ji-Hong Chiang, Hsin-Yu Chen, Hsi-Cheng Hsu
  • Publication number: 20190031503
    Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.
    Type: Application
    Filed: February 23, 2018
    Publication date: January 31, 2019
    Inventors: Jui-Chun WENG, Lavanya SANAGAVARAPU, Ching-Hsiang HU, Wei-Ding WU, Shyh-Wei CHENG, Ming-De CHEN, Ji-Hong CHIANG, Hsin-Yu CHEN, Hsi-Cheng HSU
  • Publication number: 20190010047
    Abstract: The present disclosure relates to a micro-electromechanical system (MEMs) package. In some embodiments, the MEMs package has a plurality of conductive interconnect layers disposed within a dielectric structure over an upper surface of a first substrate. A heating element is electrically coupled to a semiconductor device within the first substrate by one or more of the plurality of conductive interconnect layers. The heating element is vertically separated from the first substrate by the dielectric structure. A MEMs substrate is coupled to the first substrate and has a MEMs device. A hermetically sealed chamber surrounding the MEMs device is disposed between the first substrate and the MEMs substrate. An out-gassing material is disposed laterally between the hermetically sealed chamber and the heating element.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 10, 2019
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
  • Publication number: 20180370790
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.
    Type: Application
    Filed: September 5, 2018
    Publication date: December 27, 2018
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Shiuan-Jeng Lin, Wei-Ding Wu, Ching-Hsiang Hu
  • Patent number: 10155656
    Abstract: The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Shiuan-Jeng Lin, Wei-Ding Wu, Ching-Hsiang Hu
  • Patent number: 10131536
    Abstract: The present disclosure relates to a MEMs package having a heating element configured to adjust a pressure within a hermetically sealed chamber by inducing out-gassing of into the chamber, and an associated method. In some embodiments, the MEMs package has a CMOS substrate having one or more semiconductor devices arranged within a semiconductor body. A MEMs structure is connected to the CMOS substrate and has a micro-electromechanical (MEMs) device. The CMOS substrate and the MEMs structure form a hermetically sealed chamber abutting the MEMs device. A heating element is electrically coupled to the one or more semiconductor devices and is separated from the hermetically sealed chamber by an out-gassing layer arranged along an interior surface of the hermetically sealed chamber. By operating the heating element to cause the out-gassing layer to release a gas, the pressure of the hermetically sealed chamber can be adjusted after it is formed.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
  • Patent number: 10049941
    Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Seng Shue, Tai-I Yang, Wei-Ding Wu, Ming-Tai Chung, Shao-Chi Yu
  • Patent number: 9884758
    Abstract: The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu, Yu-Jui Wu, Ching-Hsiang Hu, Ming-Tsung Chen
  • Publication number: 20170203962
    Abstract: The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.
    Type: Application
    Filed: June 15, 2016
    Publication date: July 20, 2017
    Inventors: Shyh-Wei Cheng, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu, Yu-Jui Wu, Ching-Hsiang Hu, Ming-Tsung Chen
  • Publication number: 20170107097
    Abstract: The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 20, 2017
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Shiuan-Jeng Lin, Wei-Ding Wu, Ching-Hsiang Hu
  • Publication number: 20170107100
    Abstract: The present disclosure relates to a MEMs package having a heating element configured to adjust a pressure within a hermetically sealed chamber by inducing out-gassing of into the chamber, and an associated method. In some embodiments, the MEMs package has a CMOS substrate having one or more semiconductor devices arranged within a semiconductor body. A MEMs structure is connected to the CMOS substrate and has a micro-electromechanical (MEMs) device. The CMOS substrate and the MEMs structure form a hermetically sealed chamber abutting the MEMs device. A heating element is electrically coupled to the one or more semiconductor devices and is separated from the hermetically sealed chamber by an out-gassing layer arranged along an interior surface of the hermetically sealed chamber. By operating the heating element to cause the out-gassing layer to release a gas, the pressure of the hermetically sealed chamber can be adjusted after it is formed.
    Type: Application
    Filed: June 8, 2016
    Publication date: April 20, 2017
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
  • Patent number: 9527721
    Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package with an anti-stiction layer, and an associated method of formation. In some embodiments, the MEMS package comprises a device substrate and a CMOS substrate. The device substrate comprises a MEMS device having a moveable or flexible part that is movable or flexible with respect to the device substrate. A surface of the moveable or flexible part is coated by a conformal anti-stiction layer made of polycrystalline silicon. A method for manufacturing the MEMS package is also provided.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Chao-Po Lu, Chung-Hsien Hun, Chih-Shan Chen, Chuan-Yi Ko, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
  • Publication number: 20160332863
    Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package with an anti-stiction layer, and an associated method of formation. In some embodiments, the MEMS package comprises a device substrate and a CMOS substrate. The device substrate comprises a MEMS device having a moveable or flexible part that is movable or flexible with respect to the device substrate. A surface of the moveable or flexible part is coated by a conformal anti-stiction layer made of polycrystalline silicon. A method for manufacturing the MEMS package is also provided.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Shyh-Wei Cheng, Chao-Po Lu, Chung-Hsien Hun, Chih-Shan Chen, Chuan-Yi Ko, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
  • Publication number: 20160172250
    Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: Hong-Seng Shue, Tai-I Yang, Wei-Ding Wu, Ming-Tai Chung, Shao-Chi Yu