Abstract: A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer.

Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.

Abstract: Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface.

Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.