Abstract: An one-time programmable memory cell includes: an upper electrode; an insulating layer beneath the upper electrode; and a lower electrode with electrical field enhancement structure beneath the insulating layer, wherein the electrical field enhancement structure has a least one tip portion. The one-time programmable memory cell also includes a shallow trench isolation region, disposed adjacent to the insulating layer and the lower electrode, wherein the electrical field enhancement structure is surrounded by the shallow trench isolation region and the upper electrode partially covers the shallow trench isolation region.

Abstract: An one-time programmable memory cell includes: an upper electrode; an insulating layer beneath the upper electrode; and a lower electrode with electrical field enhancement structure beneath the insulating layer, wherein the electrical field enhancement structure has a least one tip portion. The one-time programmable memory cell also includes a shallow trench isolation region, disposed adjacent to the insulating layer and the lower electrode, wherein the electrical field enhancement structure is surrounded by the shallow trench isolation region and the upper electrode partially covers the shallow trench isolation region.

Abstract: A reaction gas supply equipment of an inductive coupled plasma mass spectrometer comprises an ammonia supply end and a helium supply end and a reaction gas supply equipment, which is supplied with an ammonia supply end and a helium supply end, and the reaction gas supply equipment is provided with an ammonia mass flow meter to adjust the flow of ammonia and helium mass flow meter to adjust the flow of helium; the ammonia mass flow meter and helium mass flow meter are adjusted by the proportion of reaction gas specified by the inductive coupled plasma spectrometer, and ammonia gas is mixed with helium gas to form reaction gas, which is then provided to the inductive coupled plasma mass spectrometer; through the technical means of the prevent invention, several advantages such as the protection of detection instrument and the reduction of cost of reaction gas can be achieved.

Abstract: An apparatus for producing 3D point-cloud model of physical objects includes a rotatable platform (11), multiple patterns asymmetrically arranged on the rotatable platform (11), a background curtain (13), and an image capturing unit (12) arranged facing toward the background curtain (13). A producing method includes: placing an object (2) to be scanned on the rotatable platform (11); setting a capturing amount during one-time rotation operation; controlling the rotatable platform (11) to perform the rotation operation, and controlling the image capturing unit (12) to capture corresponding images during the rotation operation according to the capturing amount, wherein each image includes the entire object (2) and multiple of the patterns, and records corresponding global coordinates; and, performing matching on multiple features of each of the images, and constructing a 3D point-cloud model of the object (2) according to a matching result of the features and the global coordinates of each of the images.

Abstract: An apparatus for producing 3D point-cloud model of physical objects includes a rotatable platform (11), multiple patterns asymmetrically arranged on the rotatable platform (11), a background curtain (13), and an image capturing unit (12) arranged facing toward the background curtain (13). A producing method includes: placing an object (2) to be scanned on the rotatable platform (11); setting a capturing amount during one-time rotation operation; controlling the rotatable platform (11) to perform the rotation operation, and controlling the image capturing unit (12) to capture corresponding images during the rotation operation according to the capturing amount, wherein each image includes the entire object (2) and multiple of the patterns, and records corresponding global coordinates; and, performing matching on multiple features of each of the images, and constructing a 3D point-cloud model of the object (2) according to a matching result of the features and the global coordinates of each of the images.

Abstract: A secure payment device having first and second modes is provided. In the second mode, a payment procedure is activated to receive data of a payment member for a secure payment. The secure payment device includes a touch screen group, a payment unit, a central processing unit and a secure microprocessor unit. The touch screen group displays an operation interface and a secure payment interface. In the first mode, the operation interface receives a first operation instruction via the operation interface. In the second mode, the secure payment interface obtains the data of the payment member by the payment unit, receive the second operation instruction via the secure payment interface, and activate the payment function based on a comparing result of the authentication information and the data of the payment member. A secure payment method for the aforementioned secure payment device is also provided.

Abstract: Disclosed is an electric device control system comprising an electric device control system and an intelligent remote control. Each electric device is electrically connected to a light sensing device, wherein the electric device is controlled by the light sensing device. The intelligent remote control comprises a light transmitter, a first wireless communication unit and a first controller. The light transmitter provides a high energy level visible light beam to a light sensing device, to make the light sensing device provide a wireless identification signal. The first wireless communication unit receives the wireless identification signal. The first controller is electrically connected to the first wireless communication unit. The first controller controls a coding set to switch according to the wireless identification signal, and controls the first wireless communication unit according to the coding set to output a wireless control signal to the light sensing device for controlling the electric device.

Abstract: The invention provides a voltage regulator including a transient voltage suppressor. The transient voltage suppressor includes N first transistors and N semiconductor units. The N first transistors are coupled between a reference ground and N pads respectively, and the N transistors are controlled by a voltage on a reference power line. The N semiconductor units are coupled between the reference ground and the N pads respectively, or coupled between the reference power line and the N pads respectively. N is a positive integer.

Abstract: The present disclosure provides a rectifier. The rectifier includes a N-type epitaxial layer, a plurality of P-type diffusion regions and a plurality of N-type diffusion regions. The P-type diffusion regions are disposed in the N-type epitaxial layer, and the N-type diffusion regions are respectively disposed in the P-type diffusion regions. Wherein, the P-type diffusion regions are electronically coupled to the N-type diffusion regions.

Abstract: The invention provides a voltage regulator including a transient voltage suppressor. The transient voltage suppressor includes N first transistors and N semiconductor units. The N first transistors are coupled between a reference ground and N pads respectively, and the N transistors are controlled by a voltage on a reference power line. The N semiconductor units are coupled between the reference ground and the N pads respectively, or coupled between the reference power line and the N pads respectively. N is a positive integer.

Abstract: The present disclosure provides a rectifier. The rectifier includes a N-type epitaxial layer, a plurality of P-type diffusion regions and a plurality of N-type diffusion regions. The P-type diffusion regions are disposed in the N-type epitaxial layer, and the N-type diffusion regions are respectively disposed in the P-type diffusion regions. Wherein, the P-type diffusion regions are electronically coupled to the N-type diffusion regions.

Abstract: The present invention relates to photo processing. Disclosed is a method for processing photos from multiple sources and its apparatus. In the present invention, the method of processing photos from multiple sources include: obtaining photo files from at least two sources; for the obtained photo files, merging the photo files originating from the same primitive photo into one photo object for post-processing in the unit of photo objects, each photo object contains pointer(s) to the photo file(s) corresponding with the photo object. In the present invention, while substantial contents of photo files from different sources are identical, the photo files are merged into one photo object, then users can operate in the unit of photo objects, a system automatically processes respective files of the photo objects according to different operation types, and users do not need to care about the detail of the level of the photo files, such as the sources of the photo files etc., which simplifies the user operations.

Abstract: The invention discloses an ESD protection circuit, including a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively.

Abstract: The invention discloses an ESD protection circuit, including a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively.

Abstract: The invention discloses an ESD protection circuit, comprising a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively.

Abstract: The invention discloses an ESD protection circuit, comprising a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively.

Abstract: The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state.

Abstract: The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state.

Abstract: A protection circuit protects an integrated circuit (“IC”) from peak voltages and includes a voltage divider coupled to a silicon controlled rectifier. The voltage divider allows for adjustment of the trigger voltage, trigger current, and holding voltage of the protection circuit so that the protection circuit can conduct current after a particular voltage level has been applied to the protection circuit without accidental triggering on by, for example, noise.

Abstract: The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.