Abstract: A positive mobile iron contamination (PMIC) detection apparatus disposed on a semiconductor substrate. An active region is defined on the semiconductor substrate using field oxide layers, and an MOS transistor is disposed in the active region. The positive mobile iron contamination (PMIC) detection apparatus comprises a heating device, a temperature-taking device, and a gate. The heating device is disposed on the surfaces of the field oxide layers so as to heat the semiconductor substrate. The temperature-taking device is disposed on the surface of the heating device so as to take the temperature of the semiconductor substrate and further to be the base for adjustment. The gate is disposed above the heating device, so as to receive a bias.

Abstract: An electrostatic discharge (ESD) protection device for protecting semiconductor devices against high-voltage transients due to electrostatic discharges. It includes: (1) an N-type well formed in a P-type semiconductor layer (or P-substrate); (2) a plurality of first P+ regions formed in the P-type semiconductor layer, wherein each of the first P+ regions is connected to an input,pad and is formed inside the N-type well; (3) a plurality of second P+ regions formed in the P-type semiconductor layer, wherein each of the second P+ regions is connected to the ground, at least one of the second P+ regions is outside the N-type well, and at least one of the second P+ regions is either in the N-type well or adjacent to it; and (4) an N+ region formed outside of the N-type well.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. A plurality of current divider segments are distributed on the drain region and extend between the gate and drain contacts. The segments can be formed of polysilicon or a field oxide.

Abstract: A circuit for controlling a non-volatile memory cell having a source, a drain, a control gate, and a bulk is disclosed. The control circuit comprises a voltage source, a first charge-pumping circuit, a word-line switch, a second charge-pumping circuit, a source switch, a third charge-pumping circuit, and a bulk switch. The first charge-pumping circuit, second charge-pumping circuit and third charge-pumping circuit respectively generate a first positive voltage, second positive voltage and negative voltage in response to the voltage source. The word-line switch selects and applies one of the voltage source or the first positive voltage to the control gate. The source switch selects and applies one of a ground potential or the second positive voltage to the source. The bulk switch selects and applies one of the ground potential or the negative voltage to the bulk.

Abstract: The output buffer of the present invention comprises a pull up circuit and a pull down circuit. The pull up circuit is coupled between a first power line and a pad. The pull down circuit coupled between a second power line and the pad is comprised of a resistor, a diode and an electrostatic discharge protection component. The resistor deposited on the substrate of a first conductivity type is comprised of a well region of a second conductivity type and has a first end and a second end. The first end is a forth doped region of the second conductivity type and coupled to the pad. The diode is formed in the well region, construct by the PN junction formed between a first doped region of the first conductivity type and the well region. The electrostatic discharge component is coupled between the second end and the second power line. The first doped region is electrically floated in the well regions.

Abstract: A method of fabricating an on-chip inductor is disclosed. First, a semiconductor substrate is patterned and etched to form a trench into which an insulating layer is filled. The insulating layer is provided with a relative permitivity smaller than silicon oxide or a relative permeability greater than silicon oxide. Then, a spiral conductive coil is formed over the insulating layer.

Abstract: An ESD protection circuit for protecting a circuit, comprising a lateral semiconductor-controlled rectifier, a MOS transistor, and a current-sinking device. The lateral semiconductor-controlled rectifier is coupled to the circuit and provided with a first common region and a second common region. The MOS transistor integrated with the lateral semiconductor-controlled rectifier includes the first common region The current-sinking device integrated with the lateral semiconductor controlled rectifier includes the second common region. The current-sinking device shunts the majority of a discharge current when the MOS transistor enters breakdown, thereby increasing the trigger current of the lateral semiconductor-controlled rectifier.

Abstract: A circuit for controlling a non-volatile memory cell having a source, a drain, a control gate, and a bulk is disclosed. The control circuit comprises a voltage source, a first charge-pumping circuit, a word-line switch, a second charge-pumping circuit, a source switch, a third charge-pumping circuit, and a bulk switch. The first charge-pumping circuit, second charge-pumping circuit and third charge-pumping circuit respectively generate a first positive voltage, second positive voltage and negative voltage in response to the voltage source. The word-line switch selects and applies one of the voltage source or the first positive voltage to the control gate. The source switch selects and applies one of a ground potential or the second positive voltage to the source. The bulk switch selects and applies one of the ground potential or the negative voltage to the bulk.

Abstract: An ESD protection circuit comprising a substrate having a first conductivity type, a well region having a second conductivity type, a first doping region having the first conductivity type, and a second doping region having the second conductivity type. The substrate is coupled to the reference potential, the well region is formed on the substrate and electrically coupled to the node, the first doping region is electrically floated on the surface of the well region, and the second doping region is disposed on the substrate and electrically coupled to the reference potential. Moreover, the electrostatic discharge current of the node provides a voltage with sufficient magnitude to breakdown the conjunction interface between the well region and the substrate, also triggering a BJT comprising the well region, substrate and the second doping region for dissipating the electrostatic discharge current.

Abstract: An SCR with a high trigger current is provided in a P-type semiconductor substrate with an N-well formed therein. In the P-type semiconductor substrate, there is provided a P-type region and an N-type region. In the N-well, there is provided another P-type region and another N-well. The P-type region and the N-type region in the P-type region as well as another P-type region formed between the P-type semiconductor substrate and the N-well are connected to serve as a cathode of the SCR circuit, while the P-type region and the N-type region in the N-well are connected to serve as an anode of the SCR circuit. In addition, the anode can be formed only using a P-type region, and the cathode can be formed only using an N-type region.

Abstract: A CMOS integrated circuit is formed on a P-type semiconductor layer and an N-type semiconductor layer in contact with the P-type semiconductor layer to establish a junction therebetween. A PMOS transistor is formed on the N-type semiconductor layer and configured with its source terminal connected to a first voltage source. An N-type contract region is formed in the N-type semiconductor layer and connected to the first voltage source. An NMOS transistor is formed on the P-type semiconductor layer and configured with its source terminal connected to a second voltage source. A P-type contact region is formed in the P-type semiconductor layer and connected to the second voltage source. Moreover, a P-type carrier-releasing region is provided with one portion formed in the N-type semiconductor layer and another portion formed in the P-type semiconductor layer to span the junction.

Abstract: An electrostatic discharge protection circuit triggered by a transistor having a floating base is disclosed. The electrostatic discharge protection circuit in accordance with the present invention comprises: an N-type semiconductor layer, a floating P-type semiconductor layer, a first P-type doped region, a first N-type doped region, a second N-type doped region, and a third N-type doped region. The floating P-type semiconductor layer is in contact with the N-type semiconductor layer so as to establish a junction there between. The first P-type doped region and the first N-type doped region are formed in the N-type semiconductor layer, both of which are connected to a first node. The second N-type doped region is formed in the P-type semiconductor layer and connected to a second node, while the third N-type doped region spans the junction. In addition, there is formed a gate structure overlying a portion of the P-type semiconductor layer between the second and third N-type doped regions.

Abstract: An electrostatic discharge protective circuit of the invention includes a silicon controller rectifier (SCR) and a current diverter. The current diverter is used to bypass an initial low current thereby to prevent the SCR from being triggered by the low current. Thus, a trigger current required to activate the SCR can be greatly increased thereby to maintain an internal circuit at a normal operating state.