Abstract: Systems and methods are provided for annealing a semiconductor structure using microwave radiation. A semiconductor structure is provided. One or more energy-converting materials capable of increasing the semiconductor structure's absorption of microwave radiation are provided. Microwave radiation is applied to the energy-converting materials and the semiconductor structure to anneal the semiconductor structure for fabricating semiconductor devices. First local temperatures associated with one or more first zones of the semiconductor structure are detected. The microwave radiation applied to the energy-converting materials and the semiconductor structure is adjusted based at least in part on the detected first local temperatures.

Abstract: Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation.

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.

Abstract: The invention provides a method of designing an integrated circuit. The method includes providing a physical layout group including a first layout corresponding to a first die having a first function. A second layout corresponds to an interposer configured for the first die connected thereon. The first physical layout group is partitioned into a first physical layout partition according to the first function. A first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. A first verification is performed on the first hierarchical layout.

Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a semiconductor substrate. An isolation structure is positioned in the semiconductor substrate. A first electrode and a second electrode are positioned on the semiconductor substrate and coupled to different voltage supplies. The first electrode laterally or parallelly overlaps the second electrode. The first electrode and the second electrode vertically overlap the isolation structure. As a result, leakage current is mitigated or eliminated so that the reliability and performance of the integrated circuit device are improved.

Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.

Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.

Abstract: An over-current protection device comprises a PTC device and a first external lead. The PTC device comprises first and second conductive layers and a PTC material layer laminated therebetween. The first conductive layer forms an upper surface of the PTC device. The first external lead has a lower surface soldered to the first conductive layer. The lower surface is provided with a plurality of protrusions of which tops are in direct contact with the first conductive layer to form a gap between the first external lead and the first conductive layer. Solder paste fills the gap to form an electrically conductive connecting layer. The over-current protection device may further comprise a second external lead with protrusions soldered to the second conductive layer to form an axial-lead or a radial-lead type device.

Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

Abstract: A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one feedback switch. The delay unit generates a delay signal according to an input signal and a reset signal. The cascading switch selectively passes the delay signal according to a control signal. The feedback switch selectively forms a feedback path of the delay unit according to the control signal. The decoder generates an output signal according to the delay signal. The delay unit is supplied by a work voltage. If the work voltage has noise, the noise will be detectable by analyzing the output signal of the decoder.

Abstract: Systems and methods are provided for annealing a semiconductor structure using microwave radiation. A semiconductor structure is provided. One or more energy-converting materials capable of increasing the semiconductor structure's absorption of microwave radiation are provided. Microwave radiation is applied to the energy-converting materials and the semiconductor structure to anneal the semiconductor structure for fabricating semiconductor devices. First local temperatures associated with one or more first zones of the semiconductor structure are detected. The microwave radiation applied to the energy-converting materials and the semiconductor structure is adjusted based at least in part on the detected first local temperatures.

Abstract: A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die assembled on the first surface of the packaging substrate. The semiconductor die includes a plurality of first bump pads and second bump pads on an active surface of the semiconductor die, a plurality of first copper pillars on the first bump pads, and a plurality of second copper pillars on the second bump pads. The first copper pillars have a diameter that is smaller than that of the second copper pillars.

Abstract: A method for identifying, inspecting, and reviewing all hot spots on a specimen is disclosed by using at least one SORIL e-beam tool. A full die on a semiconductor wafer is scanned by using a first identification recipe to obtain a full die image of that die and then design layout data is aligned and compared with the full die image to identify hot spots on the full die. Threshold levels used to identify hot spots can be varied and depend on the background environments close thereto, materials of the specimens, defect types, and design layout data. A second recipe is used to selectively inspect locations of all hot spots to identify killers, and then killers can be reviewed with a third recipe.

Abstract: A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode.

Abstract: A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode.

Abstract: Embodiments are directed to processing queries using schema graph traversal and to establishing a schema graph that allows queries to be answered by traversing graph nodes. In one scenario, a computer system receives a query which specifies relational tables and corresponding relationships that are to be retrieved from a relational database. The computer system accesses a schema graph that includes graph nodes representing relational tables, as well as edges that identify relationships between the relational tables. The graph nodes include relational data that was loaded from one storage area (e.g. a non-volatile storage area), and the schema graph is stored in a second storage area (e.g. a volatile storage area). The computer system then traverses the schema graph, beginning at a set of graph nodes and continuing along the edges to other graph nodes until the query has been satisfied, and then reports the results of the graph traversal.