Patents by Inventor Wei Feng

Wei Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250138000
    Abstract: Disclosed herein are highly sensitive immunoassays that utilize a capture/release mechanism to reduce non-specific binding and achieve detection with attomolar-level sensitivity. Kits that can be used for carrying out these highly sensitive immunoassays are also disclosed herein.
    Type: Application
    Filed: July 3, 2024
    Publication date: May 1, 2025
    Inventors: Yuling LUO, Wei FENG, Adrian GRZYBOWSKI, Yiyuan YIN, Shiping CHEN
  • Publication number: 20250131180
    Abstract: The present disclosure relates to a text display method, device, apparatus, and storage medium, and the method comprises: determining a length of entered text within a first container and a current width of the first container, if it is determined that the current width of the first container is less than the length of the entered text, determining a target truncated character from the entered text; then deleting characters behind the target truncated character in the entered text, and adding a preset symbol at a next position adjacent to the target truncated character to obtain a truncated text corresponding to the entered text; and displaying the truncated text in the first container.
    Type: Application
    Filed: October 28, 2022
    Publication date: April 24, 2025
    Inventors: Hongwei TANG, Wei FENG, Jun WEN
  • Publication number: 20250131895
    Abstract: A display substrate includes a base substrate having a display region and a bezel region; in the bezel region, a shift register includes an output transistor, a first electrode of the output transistor is an output end of the shift register; a patch panel is between the shift register and the display region, includes a first sub-patch panel on the same layer as the gate of the output transistor; a common electrode wire is between the shift register and the display region, there is a gap between the common electrode wire and the patch panel; a jumper includes a first sub-jumper and a second sub-jumper, the first sub-jumper is above a layer where the output transistor is, and the second sub-jumper is arranged on a different layer from the first sub-patch panel; the first sub-jumper and the first sub-patch panel overlap each other, the second sub-jumper don't overlap the gap.
    Type: Application
    Filed: September 20, 2022
    Publication date: April 24, 2025
    Inventors: Wei FENG, Xiaofang GU
  • Publication number: 20250126722
    Abstract: A circuit compensation method applied to pattern displacement includes: disposing at least one chip on a carrier; measuring a shift of the chip, performing circuit position compensation on a predetermined pattern of a redistribution layer, and calculating a resistance difference of the pattern before and after the circuit position compensation; estimating a circuit proportion and a range of resistance variation in the pattern needed for resistance compensation after the circuit position compensation according to the resistance difference; determining a compensation position and a scheme of circuit proportion and adjusting a circuit width, area, length, pattern, or combination thereof of a circuit within the circuit proportion according to the resistance difference; outputting a picture file of the pattern after the circuit position and resistance compensation; and forming the redistribution layer according to the picture file and electrically connecting the redistribution layer to the chip.
    Type: Application
    Filed: October 16, 2024
    Publication date: April 17, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Chieh-Wei Feng, Cheng-Yueh Chang, Tai-Jui Wang
  • Patent number: 12274048
    Abstract: A dynamic random access memory device includes a substrate having a first active region, a first isolation region, a second active region, and a second isolation region arranged in order along a first direction. A first bit line is disposed on the first active region and in direct contact with the first active region. A second bit line is disposed on the second isolation region. An insulating layer is disposed between and separate the second bit line and the second isolation region. A storage node contact structure is disposed between the first bit line and the second bit line and is in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: April 8, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Janbo Zhang
  • Patent number: 12264105
    Abstract: A full-fiber burner brick and a preparation method thereof, comprising mixing alumina crystal fiber and amorphous ceramic fiber with both of them being a combination of fibers of different lengths gradations, and moreover adding fine powder fillers of different particle size gradations and supplementing other additives. This enables the internal structure of the product more uniform, increases the bulk density of the product, and also benefits the suction filterability of fiber cotton blank, and is conducive to forming and improving the strength of the blank. The surface of the brick body is further provided with a coating, which can effectively protect the cotton fiber of the brick body fiber from harsh environments, improve its high temperature resistance, and help to extend the service life of the burner brick.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: April 1, 2025
    Assignee: LUYANG ENERGY-SAVING MATERIALS CO., LTD.
    Inventors: Meihua Xu, Weijin Zheng, Deli Ren, Cheng Zhang, Feng Tang, Wei Feng
  • Publication number: 20250094887
    Abstract: The present disclosure provides a method for optimizing parameters of a ladder-type carbon trading mechanism based on an improved particle swarm optimization (IPSO) algorithm. The method first obtains information and operating data of a park-level integrated energy system, establishes equipment models and constraints of the park-level integrated energy system, and establishes a ladder-type carbon trading model; then encapsulates a process of optimized low-carbon dispatching of the park-level integrated energy system as a fitness function whose input is parameters of a carbon trading mechanism and output is a carbon emission of the system; and finally, introduces an IPSO algorithm to optimize the fitness function, and outputs optimization result information of the algorithm. The present disclosure verifies effectiveness and rationality of the model and the method that give full play to a role of the ladder-type carbon trading mechanism in the park-level integrated energy system through example analysis.
    Type: Application
    Filed: October 20, 2022
    Publication date: March 20, 2025
    Inventors: Quan Chen, Xuanjun Zong, Sheng Zou, Hongwei Zhou, Tao Peng, Weiliang Wang, Wenjia Zhang, Chen Wu, Qun Zhang, Yuan Shen, Wei Feng, Gaofeng Shen, Min Zhang, Kai Yang, Xinyue Kong
  • Patent number: 12251081
    Abstract: A cavity interposer has a cavity, first bondpads adapted to couple to a chip-type camera cube disposed within a base of the cavity at a first level, the first bondpads coupled through feedthroughs to second bondpads at a base of the interposer at a second level; and third bondpads adapted to couple to a light-emitting diode (LED), the third bondpads at a third level. The third bondpads coupled to fourth bondpads at the base of the interposer at the second level; and the second and fourth bondpads couple to conductors of a cable with the first, second, and third level different. An endoscope optical includes the cavity interposer an LED, and a chip-type camera cube electrically bonded to the first bondpads; the LED is bonded to the third bondpads; and a top of the chip-type camera cube and a top of the LED are at a same level.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: March 18, 2025
    Assignee: OmniVision Technologies, Inc.
    Inventors: Teng-Sheng Chen, Wei-Ping Chen, Wei-Feng Lin, Jau-Jan Deng
  • Publication number: 20250070181
    Abstract: A fluoropolymer includes a structural unit derived from a monomer of Formula I, a structural unit derived from an olefin monomer, and a structural unit derived from a monomer of Formula II. A molar content of the structural unit derived from the monomer of Formula I is in a range of 60% to 80% based on a total mole of the structural units in the fluoropolymer, wherein R1, R2 and R3 each are independently selected from hydrogen, fluorine, chlorine, or C1-3 alkyl containing at least one fluorine atom, and R4, R5 and R6 each are independently selected from hydrogen, or substituted or unsubstituted C1-5 alkyl.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Inventors: Wei FENG, Huihui LIU, Chuying OUYANG, Chengdong SUN, Shuai ZHANG, Huanhuan ZUO, Wenshuai ZHANG, Yongbin ZHUO
  • Publication number: 20250066522
    Abstract: A core-shell polymer comprises a core portion and a shell portion that at least partially covers the core portion. The core portion comprises a structural unit derived from a monomer represented by Formula I, and the shell portion comprises a structural unit derived from a monomer represented by Formula I, a structural unit derived from a monomer represented by Formula II, and a structural unit derived from a monomer represented by Formula III, wherein R1, R2 and R3 are each independently selected from hydrogen, fluorine, chlorine or C1-3 alkyl containing at least one fluorine atom, R4, R5, R6, R7, R8, R9 are each independently selected from hydrogen or substituted or unsubstituted C1-3 alkyl, and Ar is substituted or unsubstituted aryl.
    Type: Application
    Filed: November 15, 2024
    Publication date: February 27, 2025
    Inventors: Wei FENG, Huihui LIU, Chuying OUYANG, Chengdong SUN, Wenshuai ZHANG, Shuai ZHANG, Huanhuan ZUO, Yongbin ZHOU
  • Patent number: 12238335
    Abstract: Disclosed are systems and techniques for efficient real-time codec encoding of video files. In one embodiment, the techniques include obtaining a first plurality of motion vectors of a first resolution, generating a second plurality of motion vectors of a second resolution, and calculating a first cost of the motion vector using a first cost function of a first size. The techniques include selecting a subset of motion vectors of the second plurality of motion vectors, calculating a second cost using a second cost function of a second size, and generating a plurality of combined motion vectors based on the subset of motion vectors. The techniques include calculating a third cost using the second cost function of the second size, selecting a final motion vector, and generating, based on the selected final motion vector, a block of predicted pixels that approximates a block of source pixels of an image frame.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: February 25, 2025
    Assignee: NVIDIA Corporation
    Inventors: Yongmao Tang, Jianjun Chen, Junan Chen, Yonghai Wu, Zejun Hu, Wei Feng
  • Patent number: 12212487
    Abstract: The present invention discloses a LAN system, method and unit supporting dynamic self-adaptive network configuration. Through the integration of self-adaptive dynamic routing protocol with various nodes of network, the source node broadcasts and sends a message containing destination node information, and the intermediate node searches the destination node information in its connection state sheet and returns to the source node or adds its node information into the message and sends to other intermediate nodes based on the searching results, the intermediate node will modify its routing list and open the routing transfer function. The source node and the destination node will configure their routing lists respectively with the gateway and corresponding network interfaces through which the network segment of other node is reached to establish a routing connection. The system can automatically configure the network, and greatly decrease its dependence on the central node, increasing stability and reliability.
    Type: Grant
    Filed: January 30, 2022
    Date of Patent: January 28, 2025
    Assignee: Chengdu Vantron Technology Co., Ltd.
    Inventors: Bo Wei, Song Luo, Wei Feng, Junlan Duan
  • Patent number: 12206985
    Abstract: A picture shooting method and an electronic device are disclosed. The method includes: starting an under-display camera when a first picture is moved to a first region, where the first region is a screen region corresponding to a position of the under-display camera. In embodiments of this application, a user can start the under-display camera by performing a simple operation of moving a picture, which is flexible and convenient.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: January 21, 2025
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventor: Wei Feng
  • Patent number: 12200923
    Abstract: The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: January 14, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Li-Wei Feng, Yu-Cheng Tung
  • Publication number: 20250010410
    Abstract: Disclosed are a flux-cored welding strip and a welding flux used in combination for submerged arc welding of a duplex stainless steel, and preparation methods and use thereof. The flux-cored welding strip is composed of a stainless steel shell and a flux core powder, the flux core powder consisting of the following components: in percentages by mass, ferrochrome nitride: 0.70% to 1.0%, a chromium powder: 26% to 27%, a nickel powder: 4.5% to 5.5%, a molybdenum powder: 3.7% to 4.2%, a manganese powder: 2.55% to 2.65%, a copper powder: 1.45% to 1.55%, a ferrosilicon powder: 1.1% to 1.2%, a tungsten powder: 1.0% to 1.15%, a niobium powder: 0.25% to 0.35%, an aluminum powder: 0.35% to 0.55%, a rhenium powder: 0.35% to 0.40%, a lanthanum powder: 0.1% to 0.15%, and a balance being an iron powder.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Inventors: Kai XU, Pengbo WU, Xiao GUO, Wei FENG, Shubin HUO, Shaowei CHEN, Bo CHEN, Hanmin WU, Yiming MA, Laibo SUN, Chao WEI, Naiwen FANG
  • Patent number: 12188929
    Abstract: Disclosed herein are highly sensitive immunoassays that utilize a capture/release mechanism to reduce non-specific binding and achieve detection with attomolar-level sensitivity. Kits that can be used for carrying out these highly sensitive immunoassays are also disclosed herein.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: January 7, 2025
    Assignee: Alamar Biosciences, Inc.
    Inventors: Yuling Luo, Wei Feng, Adrian Grzybowski, Yiyuan Yin, Shiping Chen
  • Patent number: 12184843
    Abstract: Disclosed are techniques for compressing data of an image using multiple processing cores. The techniques include obtaining, using a first (second, etc.) processing core, a first (second, etc.) plurality of reconstructed blocks approximating source pixels of a first (second, etc.) portion of an image and filtering, using the first processing core, the first plurality of reconstructed blocks. The filtering includes enabling application of one or more filters to a first plurality of regions that include pixels of the first plurality of reconstructed blocks but not pixels of the second plurality of reconstructed blocks. The filtering further includes disabling application of the one or more filters to a second plurality of regions that include pixels of the first plurality of reconstructed blocks and pixels of the second plurality of reconstructed blocks.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: December 31, 2024
    Assignee: Nvidia Corporation
    Inventors: Yongmao Tang, Jianjun Chen, Wei Feng, Sangeun Han, Xi He
  • Publication number: 20240416979
    Abstract: The present invention relates to a method, device and storage medium for sequencing and managing rail transit line resources. The method includes the following steps: step S101: analyzing a trackside line loop deadlock scenario and establishing a static deadlock prevention policy; step S102: reasonably making an operation plan to avoid resource deadlock loop wait; step S103: applying for all required resources for each train at a time; step S104: establishing an operation task order verification mechanism; and step S105: monitoring and executing an operation task. Compared with the prior art, the present invention can reduce the idle time of the line resources, improve the utilization rate of the line resources, and avoid the problems of operation deadlock and the mismatch between an actual train operation task and the operation plan.
    Type: Application
    Filed: November 30, 2022
    Publication date: December 19, 2024
    Inventors: Liang PAN, Xiaoyong WANG, Shaowen CHEN, Xiaoque LING, Wei FENG, Hao GAO, Xuan ZHANG
  • Publication number: 20240422958
    Abstract: A semiconductor device which includes a substrate, storage node pads, a capacitor structure and a supporting structure, and a forming method thereof are disclosed. The substrate includes a cell region and a periphery region. The storage node pads are disposed on the substrate and located in the cell region. The capacitor structure is disposed on the storage node pads and includes bottom electrodes in contact with the storage node pads. The supporting structure is disposed on the storage node pads and interleaved among the bottom electrodes. The supporting structure includes a first supporting layer and a second supporting layer sequentially from bottom to top. The second supporting layer includes a first thickness and a second thickness, wherein the second thickness is greater than the first thickness, and the second supporting layer with the second thickness is disposed between the cell region and the periphery region to provide improved structural support.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 19, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Li-Wei Feng
  • Patent number: 12170757
    Abstract: Disclosed are apparatuses, systems, and techniques for real-time codec encoding of video files using hardware-assisted accelerators that utilize a combination of parallel and sequential processing, in which at least a part of intra-frame block prediction is performed with parallel processing.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: December 17, 2024
    Assignee: NVIDIA Corporation
    Inventors: Ranga Ramanujam Srinivasan, Jianjun Chen, Dong Zhang, Wei Feng, Xi He