Patents by Inventor Wei Feng

Wei Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934106
    Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Yen Liu, Hui-Fang Kuo, Chian-Ting Huang, Wei-Cyuan Lo, Yung-Feng Cheng, Chung-Yi Chiu
  • Publication number: 20240088004
    Abstract: A stacked wiring structure includes a first wiring substrate and a second wiring substrate. The first wiring substrate includes a first glass substrate, multiple first conductive through vias penetrating through the first glass substrate, and a first multi-layered redistribution wiring structure disposed on the first glass substrate. The second wiring substrate includes a second glass substrate, multiple second conductive through vias penetrating through the second glass substrate, and a second multi-layered redistribution wiring structure disposed on the second glass substrate. The first conductive through vias are electrically connected to the second conductive through vias. The first glass substrate is spaced apart from the second glass substrate. The first multi-layered redistribution wiring structure is spaced apart from the second multi-layered redistribution wiring structure by the first glass substrate and the second glass substrate.
    Type: Application
    Filed: August 21, 2023
    Publication date: March 14, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Tai-Jui Wang, Jui-Wen Yang, Chieh-Wei Feng, Chih Wei Lu, Hsien-Wei Chiu
  • Publication number: 20240088681
    Abstract: The disclosed technology relates to a portable electronic device. The portable electronic device may comprise a battery, a battery controller, and a system controller. The battery controller may be configured to determine real time battery state information associated with the battery, the real time battery state information including a system load current draw, a battery age indicator, and a battery temperature. The system controller may be configured to determine a user initiated current low voltage mode state of the portable electronic device of a plurality of low voltage mode states, receive current battery state information from the battery controller, and adaptively generate a real time shutoff voltage threshold based on the current determined low voltage mode state and the current battery state information.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 14, 2024
    Inventors: Wei He, Guangyu Liu, Tianheng Feng, Tai-sik Hwang
  • Publication number: 20240083993
    Abstract: The present invention relates to bispecific anti-CCL2 antibodies binding to two different epitopes on human CCL2, pharmaceutical compositions thereof, their manufacture, and use as medicaments for the treatment of cancers, inflammatory, autoimmune and ophthalmologic diseases.
    Type: Application
    Filed: June 15, 2023
    Publication date: March 14, 2024
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Jens FISCHER, Guy GEORGES, Anton JOCHNER, Gregor JORDAN, Hubert KETTENBERGER, Joerg MOELLEKEN, Tilman SCHLOTHAUER, Georg TIEFENTHALER, Valeria RUNZA, Meher MAJETY, Martin SCHAEFER, Maria VIERT, Shu FENG, Wei Shiong Adrian HO, Siok Wan GAN, Runyi Adeline LAM, Michael GERTZ
  • Publication number: 20240085671
    Abstract: An annular light trapping component includes an inner surface, an outer surface, an object-side surface and an image-side surface. The inner surface includes multiple L-shaped annular grooves. The annular light trapping component includes multiple stripe-shaped structures in the L-shaped annular grooves. The L-shaped annular grooves include an object-side L-shaped annular groove closest to the object-side surface and an image-side L-shaped annular groove closest to the image-side surface. A bottom diameter of the image-side L-shaped annular groove is larger than a bottom diameter of the object-side L-shaped annular groove. Each L-shaped annular groove includes a first side and a second side located between the object-side surface and the image-side surface. The stripe-shaped structures are disposed on the first side or the second side. A degree of inclination between the first side and the central axis is larger than a degree of inclination between the second side and the central axis.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Ming-Ta CHOU, Cheng-Feng LIN, Wei-Hung WENG
  • Publication number: 20240088594
    Abstract: The present application provides a cable connector and an electronic device. The cable connector includes a socket and a plug; the socket is provided with an opening and a connection part for connecting with a circuit board; the plug includes a fixing member and an elastic connection member; the elastic connection member each includes a fixing part and a first elastic contact part connected with the fixing part, the fixing part being fixedly connected with the fixing member for connecting with an inner conductor of the cable; the fixing member is capable of connecting with the socket, and enables the first elastic contact part to elastically contact a signal connection contact on the circuit board through the opening to form electrical connection.
    Type: Application
    Filed: January 22, 2021
    Publication date: March 14, 2024
    Applicant: Zhuhai LinkE Technology Co., Ltd.
    Inventors: Gang Feng, Changming Wu, Yihong Qi, Wei YU
  • Patent number: 11928542
    Abstract: A system for detecting the direction of movement of an RFID tag along a path comprising two RFID portals, each of said portals being arranged to detect an RFID tag in a respective zone along the path, the zones being arranged to be effectively exclusive of one another, a RFID tag reader having an associated processor and multiple separate ports, each port being connected to one or the other of the portals, the processor being arranged to determine which portal first receives a RFID tag signal or signals and which portal subsequently receives a second signal from the same tag or tags detected by the first signal receiving portal, the processor providing a signal corresponding to a direction of movement, along the path from the first signal receiving portal to the second signal receiving portal.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: March 12, 2024
    Assignees: DJB GROUP LLC, WISTRON NEWEB CORPORATION
    Inventors: Walter D. Burnside, Wei-Feng Tsai
  • Patent number: 11926787
    Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignees: PetroChina Company Limited, CNPC Engineering Technology R&D Company Limited
    Inventors: Shuoqiong Liu, Hua Zhang, Jianzhou Jin, Ming Xu, Yongjin Yu, Fengzhong Qi, Congfeng Qu, Hong Yue, Youcheng Zheng, Wei Li, Yong Ma, Youzhi Zheng, Zhao Huang, Jinping Yuan, Zhiwei Ding, Chongfeng Zhou, Chi Zhang, Zishuai Liu, Hongfei Ji, Yuchao Guo, Xiujian Xia, Yong Li, Jiyun Shen, Huiting Liu, Yusi Feng, Bin Lyu
  • Publication number: 20240079524
    Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
  • Publication number: 20240072517
    Abstract: Provided is an elliptical multi-mesa laser structure, including a substrate layer, an N-DBR, a functional layer and a P-DBR sequentially arranged from bottom to top. The substrate layer is fixedly connected with an N contact layer. The N-DBR is fixedly connected to a top of the substrate layer, and the N contact layer is arranged around the N-DBR. A space layer is inserted in the N-DBR. The functional layer is fixedly connected to a top of the N-DBR. The P-DBR is fixedly connected to a top of the functional layer, and a top of the P-DBR is fixedly connected with a P contact layer. Another space layer is inserted into the P-DBR.
    Type: Application
    Filed: July 1, 2023
    Publication date: February 29, 2024
    Inventors: Hui LI, Jian FENG, Chuyu ZHONG, Wei MIAO, Shilong ZHAO, Zhao CHEN
  • Publication number: 20240071911
    Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.
    Type: Application
    Filed: January 31, 2023
    Publication date: February 29, 2024
    Inventors: Harry-Haklay Chuang, Wen-Tuo Huang, Li-Feng Teng, Wei-Cheng Wu, Yu-Jen Wang
  • Patent number: 11910595
    Abstract: The invention discloses a semiconductor memory device, which is characterized by comprising a substrate defining a cell region and an adjacent periphery region, a plurality of bit lines are arranged on the substrate and arranged along a first direction, each bit line comprises a conductive part, and the bit line comprises four sidewalls, and a spacer surrounds the four sidewalls of the bit line, the spacer comprises two short spacers covering two ends of the conductive part, two long spacers covering the two long sides of the conductive part, and a plurality of storage node contact isolations located between any two adjacent bit lines, at least a part of the storage node contact isolations cover directly above the spacers. The structure of the invention can improve the electrical isolation effect, preferably avoid leakage current and improve the quality of components.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 20, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang, Shih-Han Hung, Li-Wei Feng
  • Publication number: 20240051988
    Abstract: A method for enhancing a solubility of a plant protein includes: mixing a plant protein and water, and adjusting the pH value of a resulting mixture of the plant protein and water to 10-12 for dissolution of the plant protein, thereby obtaining a swollen plant protein; treating the swollen plant protein through ion exchange until the pH value of the mixture is 7-8, and filtering the mixture, to yield a first supernatant; separating the first supernatant to yield a second supernatant; and drying the second supernatant, to yield a modified plant protein whose solubility is higher than that of the raw plant protein.
    Type: Application
    Filed: December 6, 2022
    Publication date: February 15, 2024
    Inventors: Ren WANG, Zirui LU, Xuyuan LI, Pengcheng XU, Wei FENG, Tao WANG
  • Patent number: 11898083
    Abstract: The present disclosure relates to an azobenzene-graphene metal coordination solar photothermal energy storage material based on metal coordination bonds and a preparation method thereof. The method comprises the following steps: preparing reduced graphene oxide; preparing an azobenzene-graphene material; and preparing an azobenzene-graphene metal coordination solar photothermal energy storage material: dispersing the prepared azobenzene-graphene material in DMF, dissolving a certain amount of metal compound in DMF, adding the DMF solution of the metal compound into the DMF solution of the azobenzene-graphene, taking out the precipitate, washing off metal ions which do not participate in coordination, and drying the obtained product to obtain the azobenzene-graphene metal coordination solar photothermal energy storage material.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: February 13, 2024
    Inventors: Yiyu Feng, Hui Wang, Wei Feng, Huitao Yu
  • Publication number: 20240031150
    Abstract: The present disclosure provides a data processing method and apparatus, a computer device and a computer storage medium, wherein the method includes: performing blinding processing on target information to be transmitted to obtain blinded information; acquiring a plurality of pieces of first encryption information obtained by respectively performing encryption processing on the blinded information by a plurality of service participation ends; performing data fusion on the plurality of pieces of first encryption information to obtain second encryption information; and performing de-blinding processing on the second encryption information to obtain third encryption information as a ciphertext identification corresponding to the target information.
    Type: Application
    Filed: January 25, 2022
    Publication date: January 25, 2024
    Inventors: Peixuan HE, Baozeng DING, Quanwei CAI, Ye WU, Wei FENG
  • Patent number: 11878271
    Abstract: A low-pressure high-flux hollow fiber nanofiltration (NF) membrane, and a preparation method and use thereof are provided. The low-pressure high-flux hollow fiber NF membrane includes a base membrane and a negatively-charged separation layer formed on a surface of the base membrane, where a material of the separation layer is a crosslinking product of a negatively-charged sulfonated polymer. The low-pressure high-flux hollow fiber NF membrane of the present disclosure solves the technical problem that the hollow fiber NF membranes in the prior art are difficult to have both high performance and low energy consumption.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: January 23, 2024
    Assignee: HARRIS MEMBRANE CLEAN TECHNOLOGY INC.
    Inventors: Jiang Wei, Chulong Chen, Wei Feng
  • Publication number: 20240022007
    Abstract: An integrated antenna device comprises a curved-surface transmitting array and an array antenna. The curved-surface transmitting army has a plurality of focuses to homogenize its radiation gains. The array antenna is arranged between the curved-surface transmitting array and the plurality of focuses. According to the control of an active RF module of the array antenna, the array antenna emits the first-order beam and performs beam scanning. The curved-surface transmitting array is used to focus the first-order beam to produce a second-order beam with high gain. The generation of the beamforming feed excitation weight of the active RF module makes the integrated antenna device have a beam scanning mechanism. The array antenna can be formed by feeder antennas A DSP dynamic groups the feeder antennas to form subarrays, the subarrays can generate different first-order beams for multi-point communications. The first-order beams can be scanned in an interleaved fashion.
    Type: Application
    Filed: October 13, 2022
    Publication date: January 18, 2024
    Inventors: HSI-TSENG CHOU, CHIH-TA YEN, QIAN-XIN AN, WEI-FENG CHEN, CHENG-LIANG SHIH
  • Publication number: 20240023229
    Abstract: An arrayed RF system includes an expandable mother circuit carrier and sub-modules implemented with RF packaged radiation structures. The sub-modules are embedded onto the mother circuit carrier through plug-in interfaces to form a replaceable and expandable co-structural structure. The mother circuit carrier receives and up-converts an input intermediate-frequency signal, thereby generating first high-frequency signals. The sub-modules are horizontally embedded on the mother circuit carrier, arranged into a one-dimensional or two-dimensional array, and electrically connected to the mother circuit carrier. The RF packaged radiation structures respectively receive first high-frequency signals, thereby emitting first RF signals. The RF packaged radiation structures receive second RF signals, thereby generating second high-frequency signals. The mother circuit carrier down-converts the second high-frequency signals, thereby generating an output intermediate-frequency signal.
    Type: Application
    Filed: September 14, 2022
    Publication date: January 18, 2024
    Inventors: HSI-TSENG CHOU, CHIH-TA YEN, QIAN-XIN AN, WEI-FENG CHEN, CHENG-LIANG SHIH
  • Patent number: 11877433
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: January 16, 2024
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20240012188
    Abstract: Disclosed is a patterned optical film, comprising a patterned alignment layer having a plurality of striped retardation regions arranged in strips with different depths, a liquid crystal filling layer provided to cover and planarize the striped retardation regions, and a polarizing layer disposed on the liquid crystal filling layer.
    Type: Application
    Filed: May 3, 2023
    Publication date: January 11, 2024
    Applicant: BenQ Materials Corporation
    Inventors: Chen-Kuan Kuo, Chung-Yuan Cheng, Wei-Feng Xu, Cyun-Tai Hong