Patents by Inventor Wei-Hang Huang
Wei-Hang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11258007Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: GrantFiled: October 8, 2020Date of Patent: February 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 10937956Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.Type: GrantFiled: December 28, 2018Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chern-Yow Hsu, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20210043832Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: ApplicationFiled: October 8, 2020Publication date: February 11, 2021Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 10840438Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: GrantFiled: November 14, 2019Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 10825825Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.Type: GrantFiled: July 12, 2019Date of Patent: November 3, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20200083441Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 10529916Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: GrantFiled: March 20, 2017Date of Patent: January 7, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20190333926Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.Type: ApplicationFiled: July 12, 2019Publication date: October 31, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting SUNG, Chung-Chiang MIN, Wei-Hang HUANG, Shih-Chang LIU, Chia-Shiung TSAI
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Patent number: 10355011Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a control gate over a substrate and forming a dielectric layer covering the control gate. The method further includes forming a conductive layer having a first portion and a second portion over the dielectric layer. In addition, the first portion of the conductive layer is separated from the control gate by the dielectric layer. The method further includes forming an oxide layer on a top surface of the first portion of the conductive layer and removing the second portion of the conductive layer to form a memory gate.Type: GrantFiled: December 27, 2017Date of Patent: July 16, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20190140169Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Chern-Yow Hsu, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 10181558Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.Type: GrantFiled: March 10, 2017Date of Patent: January 15, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chern-Yow Hsu, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20180122820Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a control gate over a substrate and forming a dielectric layer covering the control gate. The method further includes forming a conductive layer having a first portion and a second portion over the dielectric layer. In addition, the first portion of the conductive layer is separated from the control gate by the dielectric layer. The method further includes forming an oxide layer on a top surface of the first portion of the conductive layer and removing the second portion of the conductive layer to form a memory gate.Type: ApplicationFiled: December 27, 2017Publication date: May 3, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting SUNG, Chung-Chiang MIN, Wei-Hang HUANG, Shih-Chang LIU, Chia-Shiung TSAI
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Patent number: 9859295Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.Type: GrantFiled: February 6, 2017Date of Patent: January 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20170194559Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: ApplicationFiled: March 20, 2017Publication date: July 6, 2017Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20170186946Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.Type: ApplicationFiled: March 10, 2017Publication date: June 29, 2017Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chern-Yow Hsu, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9685604Abstract: A magnetoresistive random-access memory (MRAM) cell includes a free layer having a variable magnetic polarity, wherein the free layer has a first width; a pin layer having a fixed magnetic polarity, wherein the pin layer has the first width; a barrier layer located between the pin layer and the free layer, wherein the barrier layer has a second width that is less than the first width; a top electrode layer located above the free layer, the pin layer, and the barrier layer; a bottom electrode layer located beneath the free layer, the pin layer, and the barrier layer; and a capping layer encapsulating a sidewall of the barrier layer.Type: GrantFiled: August 31, 2015Date of Patent: June 20, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hang Huang, Shih-Chang Liu
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Publication number: 20170148803Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.Type: ApplicationFiled: February 6, 2017Publication date: May 25, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting SUNG, Chung-Chiang MIN, Wei-Hang HUANG, Shih-Chang LIU, Chia-Shiung TSAI
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Patent number: 9620372Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.Type: GrantFiled: August 5, 2015Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chyi Liu, Wei-Hang Huang, Yu-Hsing Chang, Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai, Ru-Liang Lee
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Patent number: 9614145Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: GrantFiled: October 21, 2015Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9608195Abstract: A device includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.Type: GrantFiled: August 7, 2015Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hang Huang, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai