Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.

Abstract: A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction.

Abstract: A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

Abstract: A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and the large pattern. The oxide hard mask is then selectively removed.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure has a high-k dielectric layer; a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer and is non-L-shaped; and a second seal layer disposed on a sidewall of the first seal layer, wherein the second seal layer is an L-shaped seal layer.

Abstract: A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

Abstract: A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure has a high-k dielectric layer; a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer and is non-L-shaped; and a second seal layer disposed on a sidewall of the first seal layer, wherein the second seal layer is an L-shaped seal layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer; and a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer.

Abstract: A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

Abstract: A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer; and a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer.

Abstract: A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and the large pattern. The oxide hard mask is then selectively removed.

Abstract: A patterning method is provided. First, a first mask layer, a second mask layer and a patterned photoresist layer are sequentially formed on a target layer. Thereafter, the second mask layer is etched by using the patterned photoresist layer as a mask, so as to form a patterned second mask layer. Afterwards, a trimming process is performed to the patterned second mask layer. Further, the first mask layer is etched by using the trimmed patterned second mask layer as a mask, so as to form a patterned first mask layer. The patterned photoresist layer is then removed. Next, the target layer is etched by using the patterned first mask layer as a mask.

Abstract: A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate.

Abstract: A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate.