Patents by Inventor Wei-Hang Huang
Wei-Hang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9595661Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.Type: GrantFiled: July 18, 2013Date of Patent: March 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chern-Yow Hsu, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20170062699Abstract: A magnetoresistive random-access memory (MRAM) cell includes a free layer having a variable magnetic polarity, wherein the free layer has a first width; a pin layer having a fixed magnetic polarity, wherein the pin layer has the first width; a barrier layer located between the pin layer and the free layer, wherein the barrier layer has a second width that is less than the first width; a top electrode layer located above the free layer, the pin layer, and the barrier layer; a bottom electrode layer located beneath the free layer, the pin layer, and the barrier layer; and a capping layer encapsulating a sidewall of the barrier layer.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Wei-Hang Huang, Shih-Chang Liu
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Patent number: 9564448Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.Type: GrantFiled: May 21, 2015Date of Patent: February 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9397228Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.Type: GrantFiled: December 4, 2014Date of Patent: July 19, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Ming Wu, Wei-Hang Huang, Shih-Chang Liu
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Patent number: 9391085Abstract: Some embodiments of the present disclosure relate to a split gate memory cell which includes a select gate and a memory gate. The select gate has a planar upper surface disposed over a semiconductor substrate and is separated from the substrate by a gate dielectric layer. The memory gate has a planar upper surface arranged at one side of the select gate and is separated from the substrate by a charge trapping layer. The charge trapping layer extends under the memory gate. A first spacer is disposed above the memory gate and is separated from the memory gate by a first dielectric liner. The first dielectric liner extends upwardly along an upper sidewall of the charge trapping layer; and source/drain regions are disposed in the semiconductor substrate at opposite sides of the select gate and the memory gate.Type: GrantFiled: August 8, 2014Date of Patent: July 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hang Huang, Chang-Ming Wu, Shih-Chang Liu
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Publication number: 20160163876Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.Type: ApplicationFiled: December 4, 2014Publication date: June 9, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chang-Ming WU, Wei-Hang HUANG, Shih-Chang LIU
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Patent number: 9306158Abstract: A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction.Type: GrantFiled: October 2, 2015Date of Patent: April 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu, Wei-Hang Huang
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Publication number: 20160043306Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: ApplicationFiled: October 21, 2015Publication date: February 11, 2016Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20160043097Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have flat upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.Type: ApplicationFiled: August 8, 2014Publication date: February 11, 2016Inventors: Wei-Hang Huang, Chang-Ming Wu, Shih-Chang Liu
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Publication number: 20160028000Abstract: A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction.Type: ApplicationFiled: October 2, 2015Publication date: January 28, 2016Inventors: Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu, Wei-Hang Huang
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Publication number: 20150340493Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.Type: ApplicationFiled: August 5, 2015Publication date: November 26, 2015Inventors: Ming-Chyi Liu, Wei-Hang Huang, Yu-Hsing Chang, Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai, Ru-Liang Lee
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Publication number: 20150340596Abstract: A device includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.Type: ApplicationFiled: August 7, 2015Publication date: November 26, 2015Inventors: Wei-Hang Huang, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9196825Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.Type: GrantFiled: September 3, 2013Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9172033Abstract: A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction.Type: GrantFiled: July 3, 2013Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Ting Sung, Wei-Hang Huang, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9142761Abstract: A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.Type: GrantFiled: August 29, 2013Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hang Huang, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20150263015Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.Type: ApplicationFiled: May 21, 2015Publication date: September 17, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting SUNG, Chung-Chiang MIN, Wei-Hang HUANG, Shih-Chang LIU, Chia-Shiung TSAI
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Patent number: 9136393Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.Type: GrantFiled: January 17, 2014Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chyi Liu, Wei-Hang Huang, Yu-Hsing Chang, Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai, Ru-Liang Lee
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Patent number: 9048316Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.Type: GrantFiled: August 29, 2013Date of Patent: June 2, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20150137206Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.Type: ApplicationFiled: January 17, 2014Publication date: May 21, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chyi Liu, Wei-Hang Huang, Yu-Hsing Chang, Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai, Ru-Liang Lee
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Publication number: 20150061051Abstract: A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hang Huang, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai