Patents by Inventor Wei-Hao Huang

Wei-Hao Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9985123
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Publication number: 20180012975
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.
    Type: Application
    Filed: August 15, 2017
    Publication date: January 11, 2018
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Patent number: 9865593
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: January 9, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 9851542
    Abstract: An imaging lens including a first lens group, a second lens group, and an aperture stop is provided. The first lens group is disposed between an object side and an image side. The second lens group is disposed between the first lens group and the image side. The aperture stop is disposed between the first lens group and the second lens group. The imaging lens includes at least three cemented lenses, each of the cemented lenses includes at least one lens having non-zero refractive power, and at least one lens of each of the cemented lenses has an Abbe number greater than 80.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 26, 2017
    Assignee: Young Optics Inc.
    Inventors: Wei-Hao Huang, Kuo-Chuan Wang, Bing-Ju Chiang
  • Patent number: 9799550
    Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hao Huang, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai
  • Publication number: 20170293118
    Abstract: An imaging lens including a first lens group, a second lens group, and an aperture stop is provided. The first lens group is disposed between an object side and an image side. The second lens group is disposed between the first lens group and the image side. The aperture stop is disposed between the first lens group and the second lens group. The imaging lens includes at least three cemented lenses, each of the cemented lenses includes at least one lens having non-zero refractive power, and at least one lens of each of the cemented lenses has an Abbe number greater than 80.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 12, 2017
    Inventors: Wei-Hao Huang, Kuo-Chuan Wang, Bing-Ju Chiang
  • Patent number: 9773890
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: September 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Publication number: 20170263744
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 14, 2017
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Patent number: 9748349
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Wei-Hao Huang
  • Patent number: 9711411
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Shih-Fang Tzou, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Patent number: 9703083
    Abstract: A zoom lens system includes a first lens group of negative refractive power and a second lens group of positive refractive power. The first lens group includes a first lens of negative refractive power, and the second lens group is disposed between the first lens group and a reduced side and includes in order from a magnified side to the reduced side a second lens of positive refractive power, a third lens of positive refractive power, a fourth lens of negative refractive power, and a fifth lens of positive refractive power. At least one of the first lens to the fifth lens is an aspherical lens having at least one aspherical surface.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: July 11, 2017
    Assignee: Young Optics Inc.
    Inventors: Hung-You Cheng, Yu-Hung Chou, Yuan-Hung Su, Wei-Hao Huang
  • Patent number: 9698255
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: July 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Publication number: 20170133274
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.
    Type: Application
    Filed: December 8, 2015
    Publication date: May 11, 2017
    Inventors: Chia-Lin Lu, Shih-Fang Tzou, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Publication number: 20170102529
    Abstract: A zoom lens system includes a first lens group of negative refractive power and a second lens group of positive refractive power. The first lens group includes a first lens of negative refractive power, and the second lens group is disposed between the first lens group and a reduced side and includes in order from a magnified side to the reduced side a second lens of positive refractive power, a third lens of positive refractive power, a fourth lens of negative refractive power, and a fifth lens of positive refractive power. At least one of the first lens to the fifth lens is an aspherical lens having at least one aspherical surface.
    Type: Application
    Filed: October 12, 2015
    Publication date: April 13, 2017
    Inventors: HUNG-YOU CHENG, YU-HUNG CHOU, YUAN-HUNG SU, WEI-HAO HUANG
  • Publication number: 20170084722
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.
    Type: Application
    Filed: October 21, 2015
    Publication date: March 23, 2017
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Publication number: 20170069528
    Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: Wei-Hao Huang, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai
  • Patent number: 9543211
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Yu-Cheng Tung, Kun-Yuan Liao, Feng-Yi Chang, En-Chiuan Liou, Wei-Hao Huang, Chih-Sen Huang, Ching-Wen Hung
  • Patent number: 9543203
    Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, En-Chiuan Liou, Chia-Hsun Tseng, Wei-Hao Huang, Yu-Ting Hung
  • Publication number: 20170004997
    Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.
    Type: Application
    Filed: July 2, 2015
    Publication date: January 5, 2017
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, En-Chiuan Liou, Chia-Hsun Tseng, Wei-Hao Huang, Yu-Ting Hung
  • Publication number: 20160377844
    Abstract: An optical lens system includes, in order from a magnified side to a minified side, a first lens group and a second lens group. The first lens group of negative refractive power has at least one aspheric surface, and the second lens group of positive refractive power has at least one aspheric surface. Each of the lenses in the optical lens system is a singlet lens, and the condition: TE(?=365)>70% is satisfied, where TE(?=365) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 365 nm.
    Type: Application
    Filed: December 28, 2015
    Publication date: December 29, 2016
    Inventors: Hung-You Cheng, Yu-Hung Chou, Ching-Lung Lai, Yi-Hua Lin, Wei-Hao Huang