Patents by Inventor Wei-Hao LU
Wei-Hao LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250078814Abstract: The present disclosure provides a multi-modal encoder processing method and apparatus, a computer device and a storage medium. The method includes: acquiring a pair of mask samples to be processed, the pair of mask samples including a text sample and an audio sample associated with each other, and at least one of the text sample and the audio sample is masked; based on a multi-modal encoder, generating a text encoding feature of the text sample, and generating an audio encoding feature of the audio sample, a linear spectrum feature of the audio sample being fused in the text encoding feature, and a linear word feature of the text sample being fused in the audio encoding feature; and predicting masked mask information according to the text encoding feature and the audio encoding feature, and correcting the multi-modal encoder based on an accuracy of the mask information.Type: ApplicationFiled: August 29, 2024Publication date: March 6, 2025Inventors: Dong Guo, Zihao He, Weituo Hao, Xuchen Song, Zongyu Yin, Jingsong Gao, Wei Tsung Lu, Junyu Dai
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Patent number: 12243775Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.Type: GrantFiled: January 27, 2023Date of Patent: March 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee
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Patent number: 12237230Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.Type: GrantFiled: April 23, 2021Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Yu Lai, Jyun-Chih Lin, Yen-Ting Chen, Wei-Yang Lee, Chia-Pin Lin, Wei Hao Lu, Li-Li Su
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Patent number: 12235586Abstract: Impurities in a liquefied solid fuel utilized in a droplet generator of an extreme ultraviolet photolithography system are removed from vessels containing the liquefied solid fuel. Removal of the impurities increases the stability and predictability of droplet formation which positively impacts wafer yield and droplet generator lifetime.Type: GrantFiled: August 7, 2023Date of Patent: February 25, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hao Lai, Ming-Hsun Tsai, Hsin-Feng Chen, Wei-Shin Cheng, Yu-Kuang Sun, Cheng-Hsuan Wu, Yu-Fa Lo, Shih-Yu Tu, Jou-Hsuan Lu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
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Patent number: 12217647Abstract: An electronic device including a plurality of pixels and a driving element is provided. Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The driving element drives each first sub-pixel of the plurality of pixels.Type: GrantFiled: October 5, 2023Date of Patent: February 4, 2025Assignee: Innolux CorporationInventors: Chia-Hao Tsai, You-Cheng Lu, Yi-Shiuan Cherng, Wei-Yen Chiu
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Patent number: 12191369Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.Type: GrantFiled: September 1, 2021Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
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Publication number: 20240379781Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Wei Hao Lu, Li-Li Su, Chien-I Kuo, Yee-Chia Yeo, Wei-Yang Lee, Yu-Xuan Huang, Ching-Wei Tsai, Kuan-Lun Cheng
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Publication number: 20240300405Abstract: An electronic device including a first light source, a second light source, and a light guiding element is provided. The first light source provides a first light. The second light source provides a second light. The light guiding element includes a first microstructure, a second microstructure, and a light emitting surface. The first microstructure faces the first light source. The second microstructure faces the second light source. The first microstructure includes a plurality of first grooves. The first light enters the light guiding element through the first grooves, and exits the light guiding element via the light emitting surface. The second microstructure includes a plurality of second grooves. The second light enters the light guiding element through the second grooves, and exits the light guiding element via the light emitting surface.Type: ApplicationFiled: February 7, 2024Publication date: September 12, 2024Inventors: Wei-Hao LU, Wei-Hung LIAO, Hsin-Fu WANG
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Publication number: 20240266398Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.Type: ApplicationFiled: April 16, 2024Publication date: August 8, 2024Inventors: Chien-I Kuo, Wei Hao Lu, Li-Li Su, Yee-Chia Yeo
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Patent number: 11990511Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.Type: GrantFiled: August 27, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-I Kuo, Wei Hao Lu, Li-Li Su, Yee-Chia Yeo
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Publication number: 20230395434Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.Type: ApplicationFiled: August 10, 2023Publication date: December 7, 2023Inventors: Bo-Yu Lai, Jyun-Chih Lin, Yen-Ting Chen, Wei-Yang Lee, Chia-Pin Lin, Wei Hao Lu, Li-Li Su
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Publication number: 20230378176Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Wei Hao Lu, Yi-Fang Pai, Cheng-Wen Cheng, Li-Li Su, Chien-I Kuo
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Publication number: 20230378304Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.Type: ApplicationFiled: August 2, 2023Publication date: November 23, 2023Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
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Patent number: 11804487Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with a top surface of an STI region.Type: GrantFiled: April 4, 2022Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei Hao Lu, Yi-Fang Pai, Cheng-Wen Cheng, Li-Li Su, Chien-I Kuo
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Publication number: 20230343855Abstract: A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.Type: ApplicationFiled: June 23, 2023Publication date: October 26, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Hao LU, Chien-I KUO, Li-Li SU, Wei-Yang LEE, Yee-Chia YEO
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Publication number: 20230317785Abstract: A device includes a first nanostructure over a substrate and a first source/drain region adjacent the first nanostructure. The first source/drain region includes a first epitaxial layer covering a first sidewall of the first nanostructure. The first epitaxial layer has a first concentration of a first dopant. The first epitaxial layer has a round convex profile opposite the first sidewall of the first nanostructure in a cross-sectional view. The first source/drain region further includes a second epitaxial layer covering the round convex profile of the first epitaxial layer in the cross-sectional view. The second epitaxial layer has a second concentration of the first dopant, the second concentration being different from the first concentration.Type: ApplicationFiled: April 4, 2022Publication date: October 5, 2023Inventors: Yung-Chun Yang, Wei Hao Lu, Wei-Min Liu, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
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Publication number: 20230215935Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.Type: ApplicationFiled: March 3, 2023Publication date: July 6, 2023Inventors: Tzu-Ching Lin, Wei Te Chiang, Wei Hao Lu, Chii-Horng Li, Chien-I Kuo, Li-Li Su
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Patent number: 11688793Abstract: A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.Type: GrantFiled: April 8, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Hao Lu, Chien-I Kuo, LI-Li Su, Wei-Yang Lee, Yee-Chia Yeo
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Patent number: 11600715Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.Type: GrantFiled: October 21, 2019Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
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Publication number: 20230068434Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Chien-I Kuo, Wei Hao Lu, Li-Li Su, Yee-Chia Yeo