Patents by Inventor Wei-Hao LU
Wei-Hao LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220320307Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.Type: ApplicationFiled: September 1, 2021Publication date: October 6, 2022Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Yee-Chia Yeo, Wei Hao Lu
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Publication number: 20220231019Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with a top surface of an STI region.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Wei Hao Lu, Yi-Fang Pai, Cheng-Wen Cheng, Li-Li Su, Chien-I Kuo
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Publication number: 20220122893Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.Type: ApplicationFiled: April 23, 2021Publication date: April 21, 2022Inventors: Bo-Yu Lai, Jyun-Chih Lin, Yen-Ting Chen, Wei-Yang Lee, Chia-Pin Lin, Wei Hao Lu, Li-Li Su
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Patent number: 11296080Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with a top surface of an STI region.Type: GrantFiled: June 15, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Hao Lu, Yi-Fang Pai, Cheng-Wen Cheng, Li-Li Su, Chien-I Kuo
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Patent number: 11205713Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.Type: GrantFiled: November 30, 2018Date of Patent: December 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
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Publication number: 20210391324Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with the lowest point of the epitaxial source/drain region.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Wei Hao Lu, Yi-Fang Pai, Cheng-Wen Cheng, Li-Li Su, Chien-I Kuo
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Publication number: 20210273102Abstract: A device includes a fin extending from a substrate; a gate stack over and along sidewalls of the fin; a gate spacer along a sidewall of the gate stack; an epitaxial source/drain region in the fin and adjacent the gate spacer, the epitaxial source/drain region including a first epitaxial layer on the fin, the first epitaxial layer including silicon and arsenic; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin; and a contact plug on the second epitaxial layer.Type: ApplicationFiled: July 28, 2020Publication date: September 2, 2021Inventors: Li-Li Su, Wei-Min Liu, Wei-Hao Lu, Chien-l Kuo, Yee-chia Yeo
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Patent number: 10861935Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.Type: GrantFiled: August 5, 2019Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su, Wei Hao Lu, Wei Te Chiang, Chii-Horng Li
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Patent number: 10598619Abstract: A thermal properties measuring device is for measuring a thermal property of an object to be measured. The thermal properties measuring device includes a heating element, a measurement window, and at least one thermometer. The heating element is configured to be heated to a first temperature. The measurement window and the heating element are disposed according to a specific geometric relationship. The measurement window is configured to provide a heat transfer path between the object and the heating element. The thermometer is configured to measure an initial temperature of the to-be-measured object, and to measure a measured temperature after the heating element is heated. The measured temperature of the object is different from the initial temperature of the object. The thermal property of the object is associated with the specific geometric relationship, the first temperature, the initial temperature, the measured temperature and an environment temperature.Type: GrantFiled: December 4, 2017Date of Patent: March 24, 2020Assignee: Chung Yuan Christian UniversityInventors: Po-Ting Lin, Shu-Ping Lin, Wei-Hao Lu, Yu-Hsien Tu
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Publication number: 20200052098Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.Type: ApplicationFiled: October 21, 2019Publication date: February 13, 2020Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
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Publication number: 20190355816Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.Type: ApplicationFiled: August 5, 2019Publication date: November 21, 2019Inventors: Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su, Wei Hao Lu, Wei Te Chiang, Chii-Horng Li
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Patent number: 10453943Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.Type: GrantFiled: July 3, 2017Date of Patent: October 22, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
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Patent number: 10374038Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.Type: GrantFiled: March 15, 2018Date of Patent: August 6, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-I Kuo, Chii-Horng Li, Chia-Ling Chan, Li-Li Su, Yi-Fang Pai, Wei Te Chiang, Shao-Fu Fu, Wei Hao Lu
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Patent number: 10340190Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.Type: GrantFiled: November 24, 2017Date of Patent: July 2, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hao Lu, Yi-Fang Pai, Tuoh-Bin Ng, Li-Li Su, Chii-Horng Li
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Publication number: 20190165100Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.Type: ApplicationFiled: March 15, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-I KUO, Chii-Horng LI, Chia-Ling CHAN, Li-Li SU, Yi-Fang PAI, Wei Te CHIANG, Shao-Fu FU, Wei Hao LU
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Publication number: 20190164835Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.Type: ApplicationFiled: November 24, 2017Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hao LU, Yi-Fang PAI, Tuoh-Bin NG, Li-Li SU, Chii-Horng LI
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Publication number: 20190109217Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
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Publication number: 20180372659Abstract: A thermal properties measuring device is for measuring a thermal property of an object to be measured. The thermal properties measuring device includes a heating element, a measurement window, and at least one thermometer. The heating element is configured to be heated to a first temperature. The measurement window and the heating element are disposed according to a specific geometric relationship. The measurement window is configured to provide a heat transfer path between the object and the heating element. The thermometer is configured to measure an initial temperature of the to-be-measured object, and to measure a measured temperature after the heating element is heated. The measured temperature of the object is different from the initial temperature of the object. The thermal property of the object is associated with the specific geometric relationship, the first temperature, the initial temperature, the measured temperature and an environment temperature.Type: ApplicationFiled: December 4, 2017Publication date: December 27, 2018Applicant: Chung Yuan Christian UniversityInventors: Po-Ting Lin, Shu-Ping Lin, Wei-Hao Lu, Yu-Hsien Tu
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Patent number: 10021364Abstract: A method of building a stereoscopic model with Kalman filtering (KF) is provided. The method entails capturing images of the environment with a sensing device to build the stereoscopic model and then correcting a static object and a dynamic object in the environmental images with Kalman filtering to enhance the accuracy of the stereoscopic model. The prior art is a great reduction of accuracy in simultaneous localization and mapping (SLAM) in the event of increased system variation, increased complexity, or increased involved field. The method overcomes a drawback of the prior art.Type: GrantFiled: December 7, 2016Date of Patent: July 10, 2018Assignee: CHUNG YUAN CHRISTIAN UNIVERSITYInventors: Po-Ting Lin, Shu-Ping Lin, Wei-Hao Lu
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Publication number: 20180151703Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.Type: ApplicationFiled: July 3, 2017Publication date: May 31, 2018Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li