Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.

Abstract: A display device includes: a substrate having display and non-display areas; a first conductive layer including first and second sub-conductive lines; a second conductive layer including third and fourth sub-conductive lines, wherein, in the display area, the first sub-conductive line and the third sub-conductive lines cross from a top view; and a third conductive layer including third conductive lines and corresponding to the non-display area; wherein, corresponding to the non-display area, a portion of a projection of the one of the third conductive lines is overlapped with a portion of a projection of the second sub-conductive line on the substrate, and another portion of the projection of the one of the third conductive lines is overlapped with a portion of a projection of the fourth sub-conductive line on the substrate.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A UE performs a cell activation process in a wireless network. The UE calculates a first automatic gain control (AGC) setting based on downlink signals from a base station. The downlink signals include a coarse beam reference signal, a fine beam reference signal, and a conversion indication that indicates a power conversion between the coarse beam reference signal and the fine beam reference signal. The UE further calculates a second AGC setting based on the first AGC setting and the conversion indication. The UE performs a cell search using one of the first AGC setting and the second AGC setting, and performs fine time-frequency tracking using the other of the first AGC setting and the second AGC setting.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A Totem Pole PFC circuit includes at least one fast-switching leg, a slow-switching leg, and a control unit. Each fast-switching leg includes a fast-switching upper switch and a fast-switching lower switch. The slow-switching leg is coupled in parallel to the at least one fast-switching leg, and the slow-switching leg includes a slow-switching upper switch and a slow-switching lower switch. The control unit receives an AC voltage with a phase angle, and the control unit includes a current detection loop, a voltage detection loop, and a control loop. The control loop generates a second control signal assembly to respectively control the slow-switching upper switch and the slow-switching lower switch. The control loop controls the second control signal assembly to follow the phase angle, and dynamically adjusts a duty cycle of the second control signal assembly to turn on or turn off the slow-switching upper switch and the slow-switching lower switch.

Abstract: A wireless power transfer apparatus for capacitive-inductive power transfer has a primary and a secondary device separated by the conductive member. The primary device has at least two transmitter plates configured to be capacitively coupled with the conductive member to induce a current flow and generate a magnetic field in the conductive member. The secondary device is connectable to a load and provided with a receiving coil configured to be inductively coupled with the conductive member.

Abstract: The present disclosure provides an audio compression device, an audio compressing system and an audio compression method. The audio compression device comprises a first transceiver and a first processor. The first transceiver is connected to the first processor. The processor obtains an audio signal and an available bandwidth, and the processor performs an audio compression encoding on the audio signal to obtain a sample audio signal, and then compares with the audio signal and the sample audio signal to generate a residual signal, and the residual signal is transmitted according to the available bandwidth. The audio signal can be completely transmitted to an audio decompression device to reduce the distortion of the audio signal.

Abstract: Disclosed are a device and method for detecting defects of a high-voltage cable cross-bonded grounding system. The method comprises: selecting a protective grounding box of a cross-bonded grounding system, respectively connecting a signal excitation coupler to A-phase, B-phase and C-phase coaxial cables of the protective grounding box, selecting a stable signal with a frequency different from a power frequency or a field interference frequency, and testing effective current values and phases responded by the A-phase, B-phase and C-phase coaxial cables when the stable signal with the frequency F1 is injected into the A-phase, B-phase and C-phase coaxial cables of the protective grounding box in a coupled manner; and obtaining resistances and inductances of branch circuits of the cable cross-bonded grounding system by calculation according to measurement data, and determining if the cable cross-bonded grounding system has a connection defect.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: A method forming a grating device includes: providing a substrate; entering the substrate into a process chamber; and depositing a grating material on the substrate to form a grating material layer on the substrate. A refractive index of the grating material gradually changes during depositing the grating material in the process chamber. The grating material layer includes a varying refractive index.

Abstract: A display substrate, including: a flexible base substrate, a display structure layer, and a color filter layer. The flexible base substrate comprises: a first display region. The first display region comprises: at least one sub-display region and at least one light-transmissive region. The display structure layer comprises a plurality of first light-emitting units disposed on a flexible base substrate of the sub-display region. The color filter layer is arranged on a light exit side of the display structure layer and the at least one light-transmissive region. A color filter layer of the at least one light-transmissive region comprises a plurality of blue filter units, or a color filter layer of the at least one light-transmissive region includes: first red filter units, first green filter units, and first blue filter units which are periodically arranged.

Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.

Abstract: A semiconductor device may include a compound substrate and a 3-dimensional inductor structure. The compound substrate may include a front surface and a back surface. The 3-dimensional inductor structure may include a front conductive stack, a back conductive layer, and at least one through-hole structure. At least one portion of the front conductive stack may include a first conductive layer disposed on the front surface of the compound substrate, and a second conductive layer disposed on the first conductive layer. The second conductive layer has a thickness ranging between 30 micrometers and 400 micrometers. The back conductive layer is disposed on the back surface of the compound substrate. The at least one through-hole structure penetrates through the compound substrate, and electrically connects the front conductive stack to the back conductive layer.

Abstract: Drug delivery articles, resident articles, and retrieval systems e.g., for gram-level dosing, are generally provided. In some embodiments, the residence articles are configured for transesophageal administration, transesophageal retrieval, and/or gastric retention to/in a subject. In certain embodiments, the residence article includes dimensions configured for transesophageal administration with a gastric resident system. In some cases, the residence article may be configured to control drug release e.g., with zero-order drug kinetics with no potential for burst release for weeks to months. In some embodiments, the residence articles described herein comprise biocompatible materials and/or are safe for gastric retention. In certain embodiments, the residence article includes dimensions configured for transesophageal retrieval. In some cases, the residence articles described herein may comprise relatively large doses of drug (e.g., greater than or equal to 1 gram).

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a base station may transmit a plurality of physical downlink control channel (PDCCH) communications in a same PDCCH monitoring occasion in a first cell, and may transmit a plurality of physical downlink shared channel (PDSCH) communications in at least one of the first cell or a second cell. Each of the PDCCH communications schedules a respective PDSCH communication of the plurality of PDSCH communications. A PDCCH communication, of the plurality of PDCCH communications, includes an indication of a counter downlink assignment index that is based at least in part on a combination of a starting symbol and a cell in which an associated PDSCH communication is to be transmitted, a cell index of the cell in which the associated PDSCH communication is to be transmitted, and the PDCCH monitoring occasion. Numerous other aspects are provided.