MEMORY DEVICES AND METHODS OF FORMING THE SAME
The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.
The disclosed subject matter relates generally to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield.
BACKGROUNDSemiconductor devices and integrated circuit (IC) chips have found numerous applications in the fields of physics, chemistry, biology, computing, and memory devices. An example of a memory device is a non-volatile (NV) memory device. NV memory devices are programmable and have been extensively used electronic products due to its ability to retain data for long periods of time.
NV memory devices may be categorized based on their read/write mechanism.
Exemplary categories for NV memory may include resistive random-access memory (ReRAM), erasable programmable read-only memory (EPROM), flash memory, ferroelectric random-access memory (FeRAM), and magnetoresistive random-access memory (MRAM). NV memory devices may be built with device components such as transistors (e.g., fin-shaped field-effect transistors (FinFETs), ferroelectric field-effect transistors (FeFETs), complementary metal-oxide semiconductor (CMOS) transistors), and capacitors (e.g., metal-insulator-metal (MIM) capacitors).
Current-mode sensing amplifiers (CSAs) are commonly used in memory devices, which monitor “read currents” of the memory cells using reference cells to generate “reference current” for the CSAs. The reference current generated is being compared with the read current. However, it was found that resistance change NV memory devices, such as the ReRAM, have large variations in resistance. This may cause an unstable reference current (i.e., large fluctuations in the reference current) which results in a low sensing margin of the CSAs.
One possible approach of stabilizing the reference current is to program the memory device using an averaging bits technique, which may involve steps of oversampling and averaging the data output from multiple memory cells. The use of the averaging bits technique typically requires multiple memory arrays, each array comprising multiple reference cells and memory cells. However, by using multiple reference cells and memory cells, it was found that the resulting memory device became larger in size and incurred a higher manufacturing cost.
With the semiconductor industry's drive for higher density, higher performance, lower-cost devices and the implementation of nanometer-scale process nodes, there is a need to provide memory devices that can overcome, or at least ameliorate, one or more of the disadvantages as described above.
SUMMARYIn an aspect of the present disclosure, there is provided a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.
In another aspect of the present disclosure, there is provided a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.
In yet another aspect of the present disclosure, there is provided a method of forming a memory device by forming a first conductor layer above a substrate, forming a switching element on the first conductor layer, forming a second conductor layer above the switching element, and patterning the first conductor layer, the switching element, and the second conductor layer to form a main cell structure and a reference cell structure being electrically coupled to the main cell structure, where the reference cell structure is formed with a dimension that is different from a dimension of the main cell structure.
The present disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings.
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the present disclosure. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the present disclosure. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.
Various illustrative embodiments of the present disclosure are described below. The embodiments disclosed herein are exemplary and not intended to be exhaustive or limiting to the present disclosure.
Referring to
The reference cell structure 110 may include a switching element 104a arranged between a pair of conductors 102a and 106a in a vertically stacked configuration. Similarly, the main cell structure 112 may include a switching element 104b arranged between a pair of conductors 102b and 106b in a vertically stacked configuration. For example, as shown in
As shown in
The reference cell structure 110 has a dimension that is different from a dimension of the main cell structure 112. The dimensions of the reference cell structure 110 and the main cell structure 112 may be a thickness dimension 138, 140 or a width dimension 142, 144. The thickness dimension 138, 140 is taken as the distance between a top surface and a bottom surface of a cell structure, as shown in
In the embodiment shown in
Referring to
By having a larger width dimension, the surface area contact between the components in the reference cell structure 110 (e.g., bottom conductor, top conductor, switching element) can be increased, thereby reducing the intrinsic electrical resistance property of the reference cell structure 110 relative to the main cell structure 112. Accordingly, the reduction in the electrical resistance is found to stabilize the reference cell, which enlarges or widens the sensing margin of the sensing amplifier 168 in the memory device.
Referring to
Example of active components may include diodes (e.g., single-photon avalanche diode) or transistors such as, but not limited to, planar field-effect transistor, fin-shaped field-effect transistors (FinFETs), ferroelectric field-effect transistors (FeFETs), complementary metal-oxide semiconductor (CMOS) transistors, and bi-polar junction transistors (BJT). Although the accompanying drawings illustrate the integration of the main cell structure 112 and the reference cell structure 110 with a planar field-effect transistor, it should be understood that other active components are also contemplated within the scope of the present disclosure.
As shown in
The gate 118 and the vias 124 connecting the source or drain regions 120a, 120b may be embedded in a first inter-metal dielectric (IMD) layer 132 disposed upon the substrate 130. A second IMD layer 134 may be disposed upon the first IMD layer 132. The bottom conductor 102a of the reference cell structure 110 and the bottom conductor 102b of the main cell structure 112 may be disposed on bottom vias 114a, 114b. The bottom vias 114a, 114b are embedded within the second IMD layer 134.
Top vias 116a, 116b may be disposed on the capping layer 108a of the reference cell structure 110 and the capping layer 108b of the main cell structure 112. The reference cell structure 110, the main cell structure 112 and the top vias 116a, 116b may be embedded in a third IMD layer 136 disposed upon the second IMD layer 134. Additionally, conductive lines 128 are disposed upon the third IMD layer 136 and connected to the top vias 116a, 116b.
As shown, the bottom conductor 302 is disposed on the bottom via 314. The switching element 304 may include at least one dielectric layer. For example, the switching element 304 has three dielectric layers 346, 348, 350. Alternatively, the switching element is a single dielectric layer, as shown in
The top conductor 306 is disposed on the switching element 304. The bottom conductor 302 and the top conductor 306 includes a conductive material such as, but not limited to, titanium, titanium nitride, tantalum, tantalum nitride, and platinum.
The switching element 304 is configured to have a switchable resistance in response to a change in voltage between the pair of conductors, e.g., the bottom conductor 302 and the top conductor 306. Ideally, the switching element 304 may exhibit resistive changing properties characterized by different resistive states of the material forming this layer. These resistive states (e.g., a high resistive state or a low resistive state) may be used to represent one or more bits of information. During operational switching used to change the stored data, the switching element changes its resistive state when a certain switching voltage (e.g., a set voltage or a reset voltage) is applied to the switching element and generates a switching current through the switching element.
The capping layer 308 may serve as a protective layer for the top conductor 106. The capping layer 308 is disposed on the top conductor 106 and may include a metallic compound capable of conducting electricity. Some examples of metallic compounds for the capping layer 308 may include, but not limited to, titanium, aluminum, tantalum, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof. The top via 316 is disposed on the capping layer 308.
Advantageously, the memory devices of the present disclosure may stabilize the reference cell of the memory device and therefore enlarges its sensing margin and providing higher sensing yield. Additionally, the memory device of the present disclosure does not require multiple reference cells and memory cells to achieve an enlarged sensing margin and therefore having smaller sizes as compared to conventional memory devices. More advantageously, the present disclosure may provide a reduced intrinsic resistance of the reference cell structure as compared to the intrinsic resistance of the main cell structure, which may enable the stabilization of the reference cell during device operation.
Referring to
As used herein, “deposition techniques” refer to the process of applying a material over another material (or the substrate). Exemplary techniques for deposition include, but not limited to, spin-on coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD).
Additionally, “patterning techniques” includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described pattern, structure or opening. Examples of techniques for patterning include, but not limited to, wet etch lithographic processes, dry etch lithographic processes or direct patterning processes. Such techniques may use mask sets and mask layers.
The second conductor layer 156 is patterned to form the top conductor 106a of the reference cell structure 110, whereas the third conductor layer 162 is patterned to form the top conductor 106b of the main cell structure 112. Additionally, the first capping layer 158 is patterned to form the capping layer 108a of the reference cell structure 110, whereas the second capping layer 164 is patterned to form the capping layer 108b of the main cell structure 112. In the embodiment shown in
The structure shown in
Throughout this disclosure, the terms top, upper, upwards, over, and above refer to the direction away from the IMD layer 134 or the substrate 130. Likewise, the terms bottom, lower, downwards, under, and below refer to the direction towards the IMD layer 134 or the substrate 130. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Similarly, if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in an embodiment” herein do not necessarily all refer to the same embodiment.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description.
Additionally, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the manufacture of integrated circuits are well-known and so, in the interest of brevity, many processes are only mentioned briefly herein or omitted entirely without providing the well-known process details.
As will be readily apparent to those skilled in the art upon a complete reading of the present application, the disclosed semiconductor devices and methods of forming the same may be employed in manufacturing a variety of different integrated circuit products, including, but not limited to, memory cells, NV memory devices, FinFET transistor devices, CMOS devices, etc.
Claims
1. A memory device comprising:
- a main cell structure having a dimension; and
- a reference cell structure electrically coupled to the main cell structure, the reference cell structure having a dimension different from the dimension of the main cell structure,
- wherein the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.
2. The device of claim 1, wherein the reference cell structure has a smaller thickness dimension than the main cell structure.
3. The device of claim 1, wherein the reference cell structure has a larger width dimension than the main cell structure.
4. The device of claim 3, wherein the width dimension of the reference cell structure is larger than the width dimension of the main cell structure by a factor in the range of 1.5 to 5.
5. The device of claim 1, wherein the switching element is configured to have a switchable resistance in response to a change in voltage between the pair of conductors.
6. The device of claim 1, wherein the switching element includes at least one dielectric layer.
7. The device of claim 1, further comprising a main array having a plurality of the main cell structures, each of the main cell structure being electrically coupled to the reference cell structure.
8. The device of claim 1, wherein the switching element is arranged between a bottom conductor and a top conductor, and further comprising a capping layer disposed on the top conductor.
9. The device of claim 1, wherein the main cell structure is electrically coupled to the reference cell structure by a sensing amplifier.
10. The device of claim 1, wherein the main cell structure is configured to generate a read current and the reference cell structure is configured to generate a reference current for comparison with the generated read current.
11. The device of claim 1, wherein the reference cell structure has a lower resistance than the main cell structure.
12. A memory device comprising:
- a main cell structure including a switching element arranged between a pair of conductors; and
- a reference cell structure electrically coupled to the main cell structure, the reference cell structure including a switching element arranged between a pair of conductors, wherein the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.
13. The device of claim 12, wherein the switching element of the reference cell structure has a smaller thickness dimension than the switching element of the main cell structure.
14. The device of claim 13, wherein the thickness dimension of the switching element of the reference cell structure is smaller than the thickness dimension of the switching element of the main cell structure by a factor of 1.5 to 2.
15. The device of claim 12, wherein the switching element of the reference cell structure has a larger width dimension than the switching element of the main cell structure.
16. A method of forming a memory device comprising:
- forming a first conductor layer above a substrate;
- forming a switching element on the first conductor layer;
- forming a second conductor layer above the switching element; and
- patterning the first conductor layer, the switching element, and the second conductor layer to form a main cell structure and a reference cell structure being electrically coupled to the main cell structure, wherein the reference cell structure is formed with a dimension that is different from a dimension of the main cell structure.
17. The method of claim 16, wherein the patterning forms the reference cell structure with a smaller thickness dimension than the main cell structure.
18. The method of claim 16, wherein the patterning forms the reference cell structure with a larger width dimension than the main cell structure.
19. The method of claim 16, wherein the forming of the switching element includes deposition of at least one dielectric layer on the first conductor layer.
20. The method of claim 16, further comprising forming a capping layer on the second conductor and consequently, patterning the first conductor layer, the switching element, the second conductor layer, and the capping layer to form the main cell structure and the reference cell structure.
Type: Application
Filed: Mar 16, 2020
Publication Date: Sep 16, 2021
Inventors: CURTIS CHUN-I HSIEH (Singapore), WEI-HUI HSU (Singapore), WANBING YI (Singapore), YI JIANG (Singapore), KAI KANG (Singapore), JUAN BOON TAN (Singapore)
Application Number: 16/820,651