Patents by Inventor Wei-Jen Chen

Wei-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210223504
    Abstract: An optical system is provided. The optical system includes an immovable part, a second movable part, a second drive mechanism, and a second circuit mechanism. The second movable part is used for connecting to a second optical element. The second movable part is movable relative to the immovable part. The second drive mechanism is used for driving the second movable part to move relative to the immovable part. The second circuit mechanism is electrically connected to the second drive mechanism.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 22, 2021
    Inventors: Chan-Jung HSU, I-Mei HUANG, Yi-Ho CHEN, Shao-Chung CHANG, Ichitai MOTO, Chen-Chi KUO, Ying-Jen WANG, Ya-Hsiu WU, Wei-Jhe SHEN, Chao-Chang HU, Che-Wei CHANG, Sin-Jhong SONG, Shu-Shan CHEN, Chih-Wei WENG, Chao-Hsi WANG
  • Patent number: 11069671
    Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11011430
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
  • Publication number: 20210134981
    Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.
    Type: Application
    Filed: December 2, 2019
    Publication date: May 6, 2021
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20210134993
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 6, 2021
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Publication number: 20210123830
    Abstract: A machine tool health monitoring method which is to use a predetermined plurality of vibration sensors on a plurality of components of a machine tool and to drive motors of the machine tool to excite the machine tool using an electronic device while the health status of the machine tool is good, and then to perform a diagnostic process to obtain a characteristic cluster consisting of a plurality of modals, and then to define the characteristic cluster as a sample health characteristic cluster. The diagnostic process includes the procedures of vibration transmissibility obtaining, singular value decomposition, curve fitting and modal establishing. In addition, excite the machine tool and proceed the diagnosis process to obtain a current health characteristic cluster. Finally, the current health characteristic cluster is compared with the sample health characteristic cluster to judge whether the machine tool is healthy or not.
    Type: Application
    Filed: March 5, 2020
    Publication date: April 29, 2021
    Inventors: CHIH-CHUN CHENG, YU-SHENG CHIU, WEN-NAN CHENG, PING-CHUN TSAI, YU-HSIN KUO, WEI-JEN CHEN, DE-SHIN LIU, CHEN-WEI CHUANG, CHIH-TA WU, WEN-PENG TSENG, WEN-CHIEH KUO
  • Publication number: 20210100887
    Abstract: A recombinant fusion protein includes a receptor associated protein 1 (RAP1), a cluster of differentiation 28 (CD28)-Pseudomonas exotoxin A translocation domain (PEt) fusion polypeptide, a legumain protein and a target peptide. The RAP1 is located at the N-terminus of the recombinant fusion protein. The CD28-PEt fusion polypeptide is located at the C-terminus of the RAP1. The legumain protein is located at the C-terminus of the CD28-PEt fusion polypeptide. The target peptide is located at the C-terminus of the legumain protein. In another embodiment of the present disclosure, an immunogenic composition is provided. The immunogenic composition including the recombinant fusion protein and an adjuvant is used for inducing specific immune responses in a subject with cancer, whereby the risk of cancer metastasis and recurrence for the subject may be successfully reduced.
    Type: Application
    Filed: September 30, 2020
    Publication date: April 8, 2021
    Applicant: Reber Genetics Co., Ltd.
    Inventors: Wei-Jen Chen, Chia-Jung Chang, Pei-Yin Wu
  • Patent number: 10958290
    Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 23, 2021
    Inventors: Wei-Jen Chen, Ju-Ya Chen, Yen-Shuo Chang, Timothy Perrin Fisher-Jeffes, Mao-Ching Chiu, Cheng-Yi Hsu, Chong-You Lee
  • Publication number: 20210050441
    Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20210023149
    Abstract: The present invention provides a novel Lactobacillus fermentum strain, named Lactobacillus fermentum strain V3, and its use in manufacturing a pharmaceutical composition or a food composition for regulating intestinal microflora and treating and/or preventing an inflammatory diseases and/or a cancer.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 28, 2021
    Applicant: Syngen Biotech. Co., Ltd.
    Inventors: Wei-Jen CHEN, Shiuan-Huei WU, Chiau-Ling GUNG, Yu-Lun TSAI
  • Publication number: 20210023148
    Abstract: The present invention discloses a novel Lactobacillus brevis ProGA28, deposited in the German Collection for Microorganisms and Cell Cultures, the accession number is DSM 33167, and the deposit date is on 28 May, 2019. The metabolites of the novel Lactobacillus brevis ProGA28 has the ability to improve sleep quality, and can effectively reduce the time of rapid eye movement in sleep phase, reduce the number of falling asleep, increase the total sleep time, prolong the time of single falling asleep, and increase the ratio of low waves during sleep, so that it can achieve the effect of treating or improving sleep disorders and related complications, such as anxiety and immune system diseases.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 28, 2021
    Inventors: Wei-Jen CHEN, Bing-Huang GAU, Po-An CHEN, Yu-Shan WEI
  • Publication number: 20210023130
    Abstract: The present invention provides a novel Streptococcus thermophilus strain ST4, and its use in manufacturing a medicament and/or food composition for treating and/or preventing an inflammatory disease and/or a cancer.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 28, 2021
    Applicant: Syngen Biotech. Co., Ltd.
    Inventors: Wei-Jen Chen, Shiuan-Huei Wu, Chiau-Ling Gung, Yu-Lun Tsai
  • Publication number: 20200411649
    Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.
    Type: Application
    Filed: July 16, 2019
    Publication date: December 31, 2020
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Patent number: 10861974
    Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20200381287
    Abstract: An apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.
    Type: Application
    Filed: August 14, 2020
    Publication date: December 3, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Wei-Jen CHEN, Yi-Chen CHIANG, Tsang-Yang LIU, Chang-Sheng LEE, Wei-Chen LIAO, Wei ZHANG
  • Publication number: 20200321999
    Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 8, 2020
    Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
  • Patent number: 10790196
    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Wei-Jen Chen, Yen-Yu Chen, Ming-Hsien Lin
  • Patent number: 10790853
    Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.
    Type: Grant
    Filed: November 25, 2018
    Date of Patent: September 29, 2020
    Assignee: MEDIATEK INC.
    Inventors: Mao-Ching Chiu, Chong-You Lee, Cheng-Yi Hsu, Timothy Perrin Fisher-Jeffes, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
  • Publication number: 20200295176
    Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 17, 2020
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Patent number: 10773367
    Abstract: A nail blocking member for a nail gun. The nail gun includes a firing portion for firing a nail. When an object is pressed upon the nail blocking member by the firing portion, the nail is fired by the firing portion to enter the object. The nail blocking member includes a main body having a contact face, with a formation groove concavely disposed on the contact face, and a guiding block protruding from the formation groove. An object is pressed upon the contact face by the firing portion, and a nail is fired by the firing portion to enter the object to hit the guiding block, such that the nail is guided by the guiding block to move toward the formation groove, so as to be bent along the formation groove and reversely folded back into the object.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 15, 2020
    Assignee: EVERWIN PNEUMATIC CORPORATION
    Inventors: Wen-Sheng Huang, Wei-Jen Chen