Patents by Inventor Wei-Jen Chen

Wei-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10714347
    Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Uei Jang, Ya-Yi Tsai, Ryan Chia-Jen Chen, An Chyi Wei, Shu-Yuan Ku
  • Publication number: 20200220011
    Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; an interlayer dielectric layer disposed on the substrate; a working gate striding over the fin structure and on the first side of the trench; a dummy gate striding over the fin structure and on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region. The fin structure extends along a first direction and the dummy gate extends along a second direction. The first direction is not parallel with the second direction.
    Type: Application
    Filed: March 8, 2020
    Publication date: July 9, 2020
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20200214381
    Abstract: A wearable display device includes a wearing device, a linking-lever set, a bracket and an optical imaging device. The linking-lever set includes a first rod and a second rod, and the first rod is pivotally connected to the wearing device and the second rod, respectively. The bracket is fixedly connected to the optical imaging device, and is pivotally connected to the second rod of the at least one linking-lever set.
    Type: Application
    Filed: April 16, 2019
    Publication date: July 9, 2020
    Applicant: Quanta Computer Inc.
    Inventors: Chun-Lung CHEN, Yuan-Peng YU, Wei-Jen CHANG, Hung-Chieh WU
  • Publication number: 20200209509
    Abstract: A head-mounted display apparatus includes a wearing device, a display-source arrangement portion and an optical assembly. The wearing device has a head-wearing portion and a hat brim portion connected to the head-wearing portion. The display-source arrangement portion is connected with the hat brim portion. The optical assembly is movably disposed on the hat brim portion, and arranged between the head-wearing portion and the display-source arrangement portion.
    Type: Application
    Filed: May 8, 2019
    Publication date: July 2, 2020
    Applicant: Quanta Computer Inc.
    Inventors: Chun-Lung CHEN, Yuan-Peng YU, Wei-Jen CHANG, Hung-Chieh WU
  • Publication number: 20200205498
    Abstract: A wearable display device includes a wearing device, a fixed frame, a sliding member, a bracket and an optical imaging device. The fixed frame is fixedly connected to the wearing device. The sliding member is slidably coupled to the fixed frame. The bracket is pivotally connected to the sliding member and is interlocked with the sliding member. The optical imaging device is fixedly connected to the bracket for sliding and rotating relative to the fixed frame.
    Type: Application
    Filed: May 8, 2019
    Publication date: July 2, 2020
    Applicant: Quanta Computer Inc.
    Inventors: Chun-Lung CHEN, Yuan-Peng YU, Wei-Jen CHANG, Hung-Chieh WU
  • Publication number: 20200204295
    Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Applicant: MEDIATEK INC.
    Inventors: Chong-You LEE, Cheng-Yi Hsu, Maoching Chiu, Timothy Perrin Fisher-Jeffes, Ju-Ya Chen, Yen Shuo Chang, Wei Jen Chen
  • Publication number: 20200194321
    Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 18, 2020
    Applicant: United Microelectronics Corp.
    Inventors: KUN-YUAN WU, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
  • Patent number: 10685704
    Abstract: A static random access memory (SRAM) includes a bit cell that includes a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a write multiplexer connected to the bit information path. The write multiplexer includes a p-type transistor configured to selectively couple the bit information path to a flip-flop.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Ping-Wei Wang
  • Patent number: 10672613
    Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Uei Jang, Chien-Hua Tseng, Chung-Shu Wu, Ya-Yi Tsai, Ryan Chia-Jen Chen, An-Chyi Wei
  • Patent number: 10670784
    Abstract: A light filter structure is provided. The light filter structure includes a first filter layer disposed over the substrate. The first filter layer has a transmittance greater than 50% in a first waveband, wherein the first filter layer is an interference-type filter. The light filter structure further includes a second filter layer disposed over the substrate. The second filter layer has a transmittance greater than 50% in a second waveband, wherein the second filter layer is an absorption-type filter. The first waveband partially overlaps the second waveband at the wavelength in a third waveband, and the third waveband is in an IR region. Furthermore, an image sensor used as a time-of-flight image sensor is also provided.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 2, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Wei-Ko Wang, Yu-Jen Chen, Chia-Hui Wu
  • Patent number: 10672776
    Abstract: A memory circuit including: a first column of memory cells, each memory cell of the first column including a first supply segment; a first supply voltage line in a first conductive layer, the first supply voltage line being made of at least the first supply segments of the first column; a second supply voltage line; a first resistive device electrically connecting the first and second supply voltage lines, and being located in a via layer; a first material, from which the first resistive device is formed, being different than a second material from which a first type of via plug in the via layer is formed; and a supply voltage source electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device being in a lowest resistance path of the one or more conductive paths.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu
  • Publication number: 20200160771
    Abstract: A display device includes a plurality of pixel electrodes arranged in an array. A first switch electrically connected to a first pixel electrode of the pixel electrodes. A second switch electrically connected to a second pixel electrode of the pixel electrodes. The second switch is electrically connected between the first switch and a data line, and the first pixel electrode and the first pixel electrode are respectively located at two row of the pixel electrodes that are not adjacent to each other.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Inventors: Wei-Chien LIAO, Yu-Jen CHEN, Meng-Chieh TSAI
  • Patent number: 10659079
    Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 19, 2020
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Yi Hsu, Chong-You Lee, Wei Jen Chen, Maoching Chiu, Timothy Perrin Fisher-Jeffes, Ju-Ya Chen, Yen Shuo Chang
  • Patent number: 10658323
    Abstract: A package structure is provided. The package structure includes a semiconductor die and a protective layer surrounding the semiconductor die. The package structure also includes a conductive structure and a warpage-control element over a same side of the protective layer. A bottom surface of the warpage-control element is higher than a bottom surface of the conductive structure. The bottom surface of the warpage-control element is lower than a top surface of the conductive bump.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20200139342
    Abstract: A metal organic framework and a method for preparing the same, and an adsorption device employing the metal organic framework are provided. The metal organic framework includes a 3,5-pyridinedicarboxylic acid and a metal ion, which is an aluminum ion, a chromium ion, or a zirconium ion, wherein the 3,5-pyridinedicarboxylic acid is coordinated to the metal ion.
    Type: Application
    Filed: December 10, 2018
    Publication date: May 7, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Chih LEE, Chang-Yi SHEN, Jiun-Jen CHEN, Yuhao KANG, Shih-Yun YEN
  • Publication number: 20200139343
    Abstract: A metal organic framework and a method for preparing the same, and an adsorption device employing the metal organic framework are provided. The metal organic framework includes a 3,5-pyridinedicarboxylic acid and a metal ion, which is an aluminum ion, a chromium ion, or a zirconium ion, wherein the 3,5-pyridinedicarboxylic acid is coordinated to the metal ion.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 7, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Chih LEE, Chang-Yi SHEN, Jiun-Jen CHEN, Yuhao KANG, Shih-Yun YEN, Yu-Xuan WANG
  • Publication number: 20200135582
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
  • Publication number: 20200135472
    Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.
    Type: Application
    Filed: November 7, 2018
    Publication date: April 30, 2020
    Inventors: Shu-Uei Jang, Ya-Yi Tsai, Ryan Chia-Jen Chen, An Chyi Wei, Shu-Yuan Ku
  • Patent number: 10629734
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Patent number: 10629728
    Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; a silicon nitride trench-fill layer disposed in the trench; an interlayer dielectric layer disposed on the silicon nitride trench-fill layer; a working gate striding over the fin structure, on the first side of the trench; a dummy gate striding over the fin structure, on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee