Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A liquid color masterbatch composition for fabricating a colored fiber includes 5 parts by weight to 45 parts by weight of a colorant, 40 parts by weight to 94 parts by weight of a carrier, and 1 part by weight to 15 parts by weight of a lubricant, in which a chemical structure of the lubricant includes a carbonyl group and an amine group.

Abstract: A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

Abstract: A gate line driver is provided and includes first to second transistors and first to third switches. The first transistor and the second transistor are coupled in series between a first voltage terminal and a second voltage terminal. The first switch has a first terminal coupled to a first node between the first and second transistors. The second switch has a first terminal coupled to a third voltage terminal and a second terminal coupled to a second terminal of the first switch at a second node. The third switch has a first terminal coupled to the third voltage terminal, a second terminal coupled to the first node, and a third terminal coupled to the second node.

Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

Abstract: A method includes providing a semiconductor structure including a fin protruding from a substrate, where the fin includes first semiconductor layers and second semiconductor layers, recessing the fin to form a source/drain (S/D) recess, forming an S/D feature in the S/D recess, trimming the S/D feature, depositing a dielectric layer to cover the S/D feature, forming a contact hole in the dielectric layer to expose the S/D feature, and forming a metal contact in the contact hole.

Abstract: A liquid color masterbatch composition for fabricating a colored fiber includes 30.0 to 44.4 parts by weight of a colorant, 14.0 to 44.4 parts by weight of a lubricant, and 11.2 to 56.0 parts by weight of a carrier, in which a viscosity of the liquid color masterbatch composition between 13000 cP and 18000 cP.

Abstract: An abrasion resistance fiber includes 90.0 parts by weight to 99.0 parts by weight of a fiber body, 0.5 parts by weight to 7.5 parts by weight of an abrasion agent, 0.1 parts by weight to 0.5 parts by weight of a paraffin-based lubricant, and 0.1 parts by weight to 0.3 parts by weight of an antioxidant. The fiber body includes polyethylene terephthalate (PET). The abrasion agent is attached to a surface of the fiber body and includes silicon dioxide aerogels.

Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A liquid color masterbatch composition for fabricating a colored fiber includes 5 parts by weight to 45 parts by weight of a colorant, 40 parts by weight to 94 parts by weight of a carrier, and 1 part by weight to 15 parts by weight of a lubricant, in which a chemical structure of the lubricant includes a carbonyl group and an amine group.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A method according to the present disclosure includes depositing, over a substrate, a stack including channel layers interleaved by sacrificial layers, forming a first fin structure and a second fin in a first area and a second area of the substrate, depositing a first dummy gate stack over the first fin structure and a second dummy gate stack over the second fin structure, recessing source/drain regions of the first fin structure and second fin structure to form first source/drain trenches and second source/drain trenches, selectively and partially etching the sacrificial layers to form first inner spacer recesses and second inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, and forming second inner spacer features in the second inner spacer recesses. A composition of the first inner spacer features is different from a composition of the second inner spacer features.

Abstract: An intrinsic fluorescent green fiber includes 98.00 to 99.00 parts by weight of a carrier, 0.10 to 0.20 parts by weight of a yellow colorant, 0.08 to 0.20 parts by weight of a blue colorant, and 1.00 to 1.50 parts by weight of a titanium dioxide. When a content of 0.10 wt % to 0.20 wt % of the yellow colorant and a balance of the carrier are mixed to form a yellow fiber, the L*, a*, and b* values of the yellow fiber are respectively between 101.27 and 101.72, between ?17.61 and ?13.47, and between 89.84 and 108.79. When a content of 0.08 wt % to 0.20 wt % of the blue colorant and a balance of the carrier are mixed to form a blue fiber, the L*, a*, and b* values of the blue fiber are respectively between 55.60 and 66.80, between ?22.69 and ?22.70, and between ?37.50 and ?31.80.

Abstract: A process of heat treating an Al—Si—Cu—Mg—Fe—Zn—Mn—Sr-TMs alloy, where the TMs include Zr and V, includes heat treating the alloy to produce a microstructure having a matrix with Zr and V in solid solution after solidification. The solid solution Zr, in wt. %, is at least 0.16%, the solid solution V, in wt. %, is at least 0.20% after heat treatment, and Cu and Mg are dissolved into the matrix during the heat treatment and subsequently precipitated during the heat treatment. The composition of the alloy, in wt. %, includes Cu between 3.0-3.5%, Fe between 0-0.2%, Mg between 0.24-0.35%, Mn between 0-0.40%, Si between 6.5-8.0%, Sr between 0-0.025%, Ti between 0.05-0.2%, V between 0.20-0.35%, Zr between 0.2-0.4%, maximum 0.5% total of other alloying elements, and balance Al.

Abstract: A power supply circuit for a switching converter includes a power stage and a signal selector. The power stage has a first voltage port, a second voltage port, a third voltage port and a fourth voltage port, and has a first device terminal and a second device terminal configured to be coupled to a power storage device. The power stage includes a first switch coupled between the first voltage port and the first device terminal, a second switch coupled between the second voltage port and the second device terminal, a third switch coupled between the third voltage port and the first device terminal, and a fourth switch coupled between the fourth voltage port and the second device terminal. The signal selector, coupled to the power stage, is configured to select one of a plurality of control signals to be output to each of the first to fourth switches.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.