Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: An intrinsic fluorescent green fiber includes 98.00 to 99.00 parts by weight of a carrier, 0.10 to 0.20 parts by weight of a yellow colorant, 0.08 to 0.20 parts by weight of a blue colorant, and 1.00 to 1.50 parts by weight of a titanium dioxide. When a content of 0.10 wt % to 0.20 wt % of the yellow colorant and a balance of the carrier are mixed to form a yellow fiber, the L*, a*, and b* values of the yellow fiber are respectively between 101.27 and 101.72, between ?17.61 and ?13.47, and between 89.84 and 108.79. When a content of 0.08 wt % to 0.20 wt % of the blue colorant and a balance of the carrier are mixed to form a blue fiber, the L*, a*, and b* values of the blue fiber are respectively between 55.60 and 66.80, between ?22.69 and ?22.70, and between ?37.50 and ?31.80.

Abstract: An LED controller is used with a video source and at least one LED unit, and includes a control signal generator and a driver. The control signal generator performs pulse width modulation based on a first clock signal, a second clock signal and a data signal, which is generated by the video source, to generate at least one control signal. The first and second clock signals are independent of a vertical synchronization signal that is generated by the video source. The driver generates, based on the at least one control signal, at least one drive signal that is related to light emission of the at least one LED unit.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: A light-emitting diode driving system including a load, a power supply circuit and a light-emitting diode driving device is provided. The load includes one or more light-emitting diode strings. The power supply circuit outputs an output voltage to drive the load according to a feedback signal. The light-emitting diode driving device includes at least one current source, at least one comparator and a control logic circuit. The current source outputs a current to drive the load. The comparator compares a first voltage from the current source to a reference voltage and outputs a second voltage according to a comparison result. The control logic circuit includes a control node. The control logic circuit receives the second voltage through the control node and converts the second voltage to a control signal to adjust a resistance value of a variable resistor circuit. A light-emitting diode driving device is also provided.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: An LED controller is used with a video source and at least one LED unit, and includes a control signal generator and a driver. The control signal generator performs pulse width modulation based on a first clock signal, a second clock signal and a data signal, which is generated by the video source, to generate at least one control signal. The first and second clock signals are independent of a vertical synchronization signal that is generated by the video source. The driver generates, based on the at least one control signal, at least one drive signal that is related to light emission of the at least one LED unit.

Abstract: An LED controller is used with a video source and at least one LED unit, and includes a control signal generator and a driver. The control signal generator performs pulse width modulation based on a first clock signal, a second clock signal and a data signal, which is generated by the video source, to generate at least one control signal. The first and second clock signals are independent of a vertical synchronization signal that is generated by the video source. The driver generates, based on the at least one control signal, at least one drive signal that is related to light emission of the at least one LED unit.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A modified nylon 66 fiber including a first repeating unit derived from adipic acid and hexamethylenediamine, a second monomer unit derived from a diacid or a diamine having a long carbon chain, a third monomer unit derived from a diacid or a diamine having a aromatic ring, and a fourth monomer unit derived from a cyclic diacid or a cyclic diamine is provided. The second monomer unit has 6 to 36 carbon atoms. The third monomer unit has 8 to 14 carbon atoms. The fourth monomer unit has 6 to 10 carbon atoms. Based on a total weight of the modified nylon 66 fiber, a content of the first repeating unit is 78 wt % to 94.8 wt %, a content of the second monomer unit is 0.1 wt % to 1 wt %, a content of the third monomer unit is 5 wt % to 20 wt %, a content of the fourth monomer unit is 0.1 wt % to 1 wt %.

Abstract: A process of heat treating an Al—Si—Cu—Mg—Fe—Zn—Mn—Sr-TMs alloy, where the TMs include Zr and V, includes heat treating the alloy to produce a microstructure having a matrix with Zr and V in solid solution after solidification. The solid solution Zr, in wt. %, is at least 0.16%, the solid solution V, in wt. %, is at least 0.20% after heat treatment, and Cu and Mg are dissolved into the matrix during the heat treatment and subsequently precipitated during the heat treatment. The composition of the alloy, in wt. %, includes Cu between 3.0-3.5%, Fe between 0-0.2%, Mg between 0.24-0.35%, Mn between 0-0.40%, Si between 6.5-8.0%, Sr between 0-0.025%, Ti between 0.05-0.2%, V between 0.20-0.35%, Zr between 0.2-0.4%, maximum 0.5% total of other alloying elements, and balance Al.

Abstract: A high fatigue strength aluminum alloy comprises in weight percent copper 3.0-3.5%, iron 0-1.3%, magnesium 0.24-0.35%, manganese 0-0.8%, silicon 6.5-12.0%, strontium 0-0.025%, titanium 0.05-0.2%, vanadium 0.20-0.35%, zinc 0-3.0%, zirconium 0.2-0.4%, a maximum of 0.5% other elements and balance aluminum plus impurities. The alloy defines a microstructure having an aluminum matrix with the Zr and the V in solid solution after solidification. The matrix has solid solution Zr of at least 0.16% after heat treatment and solid solution V of at least 0.20% after heat treatment, and both Cu and Mg are dissolved into the aluminum matrix during the heat treatment and subsequently precipitated during the heat treatment. A process for heat treating an Al—Si—Cu—Mg—Fe—Zn—Mn—Sr-TMs alloy comprises heat treating the alloy to produce a microstructure having a matrix with Zr and V in solid solution after solidification.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: A light-emitting diode driving system including a load, a power supply circuit and a light-emitting diode driving device is provided. The load includes one or more light-emitting diode strings. The power supply circuit outputs an output voltage to drive the load according to a feedback signal. The light-emitting diode driving device includes at least one current source, at least one comparator and a control logic circuit. The current source outputs a current to drive the load. The comparator compares a first voltage from the current source to a reference voltage and outputs a second voltage according to a comparison result. The control logic circuit includes a control node. The control logic circuit receives the second voltage through the control node and converts the second voltage to a control signal to adjust a resistance value of a variable resistor circuit. A light-emitting diode driving device is also provided.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: A modified nylon 66 fiber including a first monomer derived from adipic acid and hexamethylenediamine, a second monomer derived from a diacid or a diamine having a long carbon chain, a third monomer derived from a diacid or a diamine having a aromatic ring, and a fourth monomer derived from a cyclic diacid or a cyclic diamine is provided. The second monomer has 6 to 36 carbon atoms. The third monomer has 8 to 14 carbon atoms. The fourth monomer has 6 to 10 carbon atoms. Based on a total weight of the modified nylon 66 fiber, a content of the first monomer is 78 wt % to 94.8 wt %, a content of the second monomer is 0.1 wt % to 1 wt %, a content of the third monomer is 5 wt % to 20 wt %, a content of the fourth monomer is 0.1 wt % to 1 wt %.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through holes and penetrate the insulator filled in the through holes. The pads are disposed on an upper surface and a lower surface of the insulator and electrically connected to the conductive vias. A bottom surface of each pad is lower than the top surface of the insulator. The patterned circuit layer is disposed on the top surface of the insulator and connected to the conductive vias and the pads. A bottom surface of the patterned circuit layer is lower than the top surface of the insulator.

Abstract: A high fatigue strength aluminum alloy comprises in weight percent copper 3.0-3.5%, iron 0-1.3%, magnesium 0.24-0.35%, manganese 0-0.8%, silicon 6.5-12.0%, strontium 0-0.025%, titanium 0.05-0.2%, vanadium 0.20-0.35%, zinc 0-3.0%, zirconium 0.2-0.4%, a maximum of 0.5% other elements and balance aluminum plus impurities. The alloy defines a microstructure having an aluminum matrix with the Zr and the V in solid solution after solidification. The matrix has solid solution Zr of at least 0.16% after heat treatment and solid solution V of at least 0.20% after heat treatment, and both Cu and Mg are dissolved into the aluminum matrix during the heat treatment and subsequently precipitated during the heat treatment. A process for heat treating an Al—Si—Cu—Mg—Fe—Zn—Mn—Sr-TMs alloy comprises heat treating the alloy to produce a microstructure having a matrix with Zr and V in solid solution after solidification.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features.