Patents by Inventor Wei Liao

Wei Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149797
    Abstract: An antenna module includes a ground radiator, a first antenna, and a second antenna. The first antenna comprises a first radiator, a second radiator, and a third radiator. The first radiator and the second radiator resonate at a low frequency band and a first high frequency band, and a part of the first radiator and the third radiator resonate at a second high frequency band. The second antenna includes a fourth radiator, the second radiator, and a connecting section. The connecting section is connected between the fourth radiator and the second radiator. A part of the fourth radiator, the connecting section, and the second radiator resonate at the low frequency band and the second high frequency band, and the fourth radiator, the connecting section, and a part of the second radiator resonate at the first high frequency band.
    Type: Application
    Filed: July 11, 2024
    Publication date: May 8, 2025
    Applicant: PEGATRON CORPORATION
    Inventors: Chao-Hsu Wu, Chien-Yi Wu, Hao-Hsiang Yang, Tse-Hsuan Wang, Chih-Wei Liao, Hau Yuen Tan, Shih-Keng Huang, Chia-Hung Chen
  • Publication number: 20250141714
    Abstract: A processing system may identify first virtual circuits and first client systems associated with a first network-to-network interface between a first communication network and a second communication network, the first network-to-network interface having a first bandwidth parameter. The processing system may next select at least a first portion of the first client systems for transfer from the first virtual circuits associated with the first network-to-network interface to second virtual circuits associated with a second network-to-network interface between the first communication network and the second communication network, the second network-to-network interface having a second bandwidth parameter. The processing system may then generate an order to establish the second virtual circuits via the second network-to-network interface and transfer the at least the first portion of the first client systems to the second virtual circuits via the second network-to-network interface.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Inventors: Dongmei Wang, Wei Liao, Marco Platania, Vijay Gopalakrishnan, Slawomir Stawiarski, Jennifer Yates
  • Publication number: 20250140684
    Abstract: A semiconductor includes a first substrate having a device region and a ring region surrounding the device region, a first interconnect structure over the first substrate, the first interconnect structure including a first via tower and a second via tower, a first bonding layer over the first interconnect structure and including a first metal bonding feature, a second bonding layer over the first bonding layer and including a second metal bonding feature in contact with the first metal bonding feature, and a second interconnect structure over the second bonding layer and including a third via tower extending through the second interconnect structure and disposed directly over the ring region. The first via tower is electrically coupled to the second via tower by a first metal line. The first via tower is electrically coupled to the third via tower by the first metal bonding feature and the second metal bonding feature.
    Type: Application
    Filed: February 13, 2024
    Publication date: May 1, 2025
    Inventors: Chi-Hui Lai, Yang-Che Chen, Hsiang-Tai Lu, Wei-Ray Lin, Tse-Wei Liao, Ming Jun Li
  • Patent number: 12282723
    Abstract: A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shi-Han Zhang, You-Cheng Lai, Jerry Chang Jui Kao, Pei-Wei Liao, Shang-Chih Hsieh, Meng-Kai Hsu, Chih-Wei Chang
  • Patent number: 12272592
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: April 8, 2025
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Patent number: 12251790
    Abstract: The embodiments of the present disclosure provide a polishing head management system and method. The polishing head management system includes: a storage device, a pick-and-place device and a data acquisition device, where the storage device is used to store polishing heads; the pick-and-place device is used to pick a polishing head or place a polishing head into the storage device; the data acquisition device is connected with the storage device and the pick-and-place device, and is used to record at least one management cycle of the polishing head.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: March 18, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Fan-Wei Liao, Chin-Chung Ku
  • Publication number: 20250087888
    Abstract: An antenna assembly includes a patch antenna, a metal layer, and a feed-in signal layer. The metal layer is disposed on a side of the patch antenna and includes a first slot and a second slot. The feed-in signal layer is disposed on a side of the metal layer opposite the second antenna and includes a transmitting port, a receiving port, a hybrid coupler, and two microstrips. The transmitting port and the receiving port are connected to the hybrid coupler, and the two microstrips are extended in the direction away from the hybrid coupler. Projections of two ends of the two microstrips onto the metal layer are overlapped with the first slot and the second slot. An antenna array is also mentioned.
    Type: Application
    Filed: May 30, 2024
    Publication date: March 13, 2025
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Tse-Hsuan Wang, Chih-Fu Chang, Hsin-Feng Hsieh, Wu-Hua Chen, Chih-Wei Liao, Chao-Hsu Wu
  • Patent number: 12237312
    Abstract: A light-emitting diode (LED) packaging module includes a plurality of LED chips spaced apart from one another, an encapsulating layer that fills in a space among the LED chips, a light-transmitting layer disposed on the encapsulating layer, a wiring assembly disposed on and electrically connected to the LED chips, and an insulation component that covers the encapsulating layer and the wiring assembly. Each of the LED chips includes an electrode assembly including first and second electrodes. The light-transmitting layer includes a light-transmitting layer that has a light transmittance greater than that of the encapsulating layer.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 25, 2025
    Assignee: QUANZHOU SANAN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Shuning Xin, Chen-Ke Hsu, Aihua Cao, Junpeng Shi, Weng-Tack Wong, Yanqiu Liao, Zhen-Duan Lin, Changchin Yu, Chi-Wei Liao, Zheng Wu, Chia-En Lee
  • Publication number: 20250060793
    Abstract: A laptop computer with a quick-release keyboard including a host, a display, and a keyboard is provided. The host has a first surface and a second surface opposite to each other. The host has at least one movable hook disposed on the first surface. The display is pivoted to the host to be folded or unfolded relative to the first surface of the host. The laptop computer is supported on a platform via the second surface when the display is unfolded relative to the first surface of the host. The keyboard has a locking column to be locked by the movable hook when the keyboard is disposed on the first surface, such that the keyboard is fixed on the first surface.
    Type: Application
    Filed: January 22, 2024
    Publication date: February 20, 2025
    Applicant: Acer Incorporated
    Inventors: Wei-Chih Wang, Chen-Min Hsiu, Chih-Wei Liao
  • Publication number: 20250063790
    Abstract: A semiconductor fabrication method includes: forming, on a substrate, an epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a fin in the epitaxial stack; forming a sacrificial gate stack on channel regions of the fin; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; performing pre-treatment operations to remove impurities from the at least one sacrificial epitaxial layer; recessing the at least one sacrificial epitaxial layer to form a cavity; forming inner spacer material in the cavity; forming source/drain features; removing the sacrificial gate stack and the at least one sacrificial epitaxial layer in the fins; and forming a metal gate to replace the sacrificial gate stack and the at least one sacrificial epitaxial layer, wherein the inner spacers have sufficient thickness to resist epi damage.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Uei Jang, Chung-Shu Wu, Ya-Wei Liao
  • Publication number: 20250062525
    Abstract: An antenna comprises a first radiation part, a second radiation part, a feed part, and a ground part. The first radiation part comprises a first radiator. The second radiation part comprises a second radiator. A first side of the feed part bends upward to form the first radiator, which is a part of the first radiation part. A second side of the feed part bends upward to form the second radiator, which is a part of the second radiation part. The first side is arranged relative to the second side. A height difference between the first radiator and the second radiator in the first direction is within a preset range. The first direction is perpendicular to a plane where the feed part is located. A vehicle is also provided.
    Type: Application
    Filed: October 9, 2023
    Publication date: February 20, 2025
    Inventors: CHING-LING WU, HSIANG-NENG WEN, YUNG-YU TAI, CHIH-WEI LIAO
  • Patent number: 12228763
    Abstract: A switchable backlight module is disclosed. The switchable backlight module includes two light source modules arranged parallelly with respect to a plane. Each of the light source modules includes a turning film and a LGP. The LGP is of an edge-lit type arranged parallelly under the turning film. A light ray enters the LGP from a light incident side of the LGP, exits the LGP from a light emergent surface of the LGP, enters the turning film, and exits the turning film from a surface of the turning film away from the LGP. The light incident side of the LGP of one of the light source modules is perpendicular to the light incident side of the LGP of the other light source module. The switchable backlight module is in an anti-peeping mode having a narrow viewing angle when only an upper one of the light source modules emits light.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: February 18, 2025
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventors: Yu-Huan Chiu, Chien-Wei Liao, Yen-Lung Chen
  • Patent number: 12230612
    Abstract: A light-emitting diode (LED) packaging module includes light-emitting units arranged in an array having m row(s) and n column(s), an encapsulating layer, and a wiring assembly, where m and n each independently represents a positive integer. Each of the light-emitting units includes LED chips each including a chip first surface, a chip second surface, a chip side surface, and an electrode assembly disposed on the chip second surface. The encapsulating layer covers the chip side surface and fills a space among the LED chips. The wiring assembly is disposed on the chip second surface and is electrically connected to the electrode assembly.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 18, 2025
    Assignee: QUANZHOU SANAN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Shuning Xin, Zhen-Duan Lin, Yanqiu Liao, Junpeng Shi, Aihua Cao, Changchin Yu, Chen-Ke Hsu, Chi-Wei Liao, Chia-En Lee, Zheng Wu
  • Patent number: 12230611
    Abstract: A light-emitting device includes a number (N) of light-emitting units, a number (a) of first metal pads and a number (b) of second metal pads. Each of the light-emitting units includes a number (n) of light-emitting chips each having two distinct terminals, where N and n are integers and N>1, n>?3. The numbers (a) and (b) are integers and a>1, b>1, and the terminals of each of the light-emitting chips are electrically connected to a unique combination of one of the number (a) of first metal pads and a number (b) of second metal pads, respectively. The numbers (N), (n), (a) and (b) satisfy the equation: a*b=n*N.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 18, 2025
    Assignee: QUANZHOU SANAN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Yanqiu Liao, Junpeng Shi, Shuning Xin, Chen-ke Hsu, Zhen-duan Lin, Changchin Yu, Aihua Cao, Chi-Wei Liao, Zheng Wu, Chia-en Lee
  • Publication number: 20250046702
    Abstract: A semiconductor structure includes an interconnect structure, a passivation structure, a first capacitor, and a contact feature. The interconnect structure is disposed over a semiconductor substrate. The passivation structure is disposed over the interconnect structure. The first capacitor is disposed within the passivation structure. The contact feature is disposed over the passivation structure, wherein the first capacitor is proximal to a corner of the contact feature. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: WEI-YU CHOU, YANG-CHE CHEN, TING-YUAN HUANG, TSE-WEI LIAO, CHENG-YU HSIEH, HSIANG-TAI LU
  • Publication number: 20250044553
    Abstract: An optical lens assembly includes a stop, and includes, in order from the object side to the image side: a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens; wherein a refractive index of the third lens is nd3, a central thickness of the third lens along the optical axis is CT3, an entrance pupil diameter of the optical lens assembly is EPD, and the following condition is satisfied: 2.64?(nd3*CT3)/EPD?4.55.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 6, 2025
    Inventor: Chia-Wei LIAO
  • Publication number: 20250043054
    Abstract: A method for manufacturing a large-particle-size styrene butadiene latex includes mixing a first styrene-butadiene latex with a polyacrylate agglomerating agent and an inorganic salt solution to allow the first styrene-butadiene latex to undergo an agglomeration process, so as to obtain a second styrene-butadiene latex that has a particle size larger than that of the first styrene-butadiene latex. The polyacrylate agglomerating agent is present in an amount ranging from 0.1 parts by weight to 1 part by weight and an inorganic salt in the inorganic salt solution is present in an amount of 0.25 parts by weight, based on 100 parts by weight of the first styrene-butadiene latex. The first styrene-butadiene latex is stable and not susceptible to emulsion breaking during the agglomeration process.
    Type: Application
    Filed: November 28, 2023
    Publication date: February 6, 2025
    Inventors: Chun-Wei LIAO, Pen-Hsin CHOU
  • Publication number: 20250037219
    Abstract: An innovative system is introduced to elevate the tourist experience, offering a single, comprehensive platform for pre-trip planning, on-site photo capturing, and during or post-trip sharing. Users can customize their itinerary through an intuitive interface, prompting the server to supply extensive information on the selected attractions, including detailed descriptions, photography guidance, and social content creation tips. Pre-trip, tourists are equipped with thorough knowledge about their tourist attractions, enhancing preparation and anticipation. During the journey, users receive on-the-spot photography guidance to maximize experience capture. During or post-trip, the system eases the process of sharing the journey across platforms. This holistic approach amplifies understanding of chosen attractions, improves documentation of experiences, and facilitates effortless sharing, profoundly augmenting the tourism experience.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Inventor: Wei Liao
  • Publication number: 20250020892
    Abstract: An optical lens assembly includes, in order from an object side to an image side: a first lens with negative refractive power; a second lens with negative refractive power; a third lens with positive refractive power; a fourth lens with positive refractive power; a fifth lens with negative refractive power; a sixth lens with positive refractive power; wherein a distance from an object-side surface of the first lens to an image plane along an optical axis is TL, an incident angle of a chief ray on the image plane at a maximum view angle of the optical lens assembly is CRA, a focal length of the optical lens assembly is f, and the following condition is satisfied: 51.73°<TL*CRA/f<129.65°.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 16, 2025
    Inventors: Chia-Wei LIAO, Chun-Sheng LEE, Chi-Chang WANG
  • Patent number: 12197070
    Abstract: The present disclosure provides a fabrication method of a light guide plate including the following steps. A first substrate with a processing plane is provided. A plurality of first mold trenches are formed along a second direction on the processing plane by a first cutter, where the first mold trenches are connected to each other. A plurality of second mold trenches are formed along a first direction different from the second direction in a first processing region of the processing plane by a second cutter, where the first processing region is near to a first edge of the processing plane. A light-emitting surface of the light guide plate is formed by using the first substrate as a mold.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: January 14, 2025
    Assignee: Darwin Precisions Corporation
    Inventors: Yu-Huan Chiu, Chien-Wei Liao, Yen-Lung Chen