Abstract: An electronic device may have a display with an array of inorganic light-emitting diodes. The array of inorganic light-emitting diodes may be overlapped by a polarizer layer such as a circular polarizer. Alternatively, the display may be a polarizer-free display without any polarizer layer over the array of inorganic light-emitting diodes. Each inorganic light-emitting diode may be surrounded by a diffuser that redirects edge-emissions towards a viewer. A top diffuser, a color filter layer, a microlens, and/or a microlens with color filtering and/or diffusive properties may also optionally overlap each inorganic light-emitting diode. The inorganic light-emitting diodes may have reflective sidewalls to mitigate edge-emissions. In this type of arrangement, the array of inorganic light-emitting diodes may be coplanar with one or more opaque masking layers. To mitigate reflections, the display may include two opaque masking layers having differing properties or a single phase separated opaque masking layer.

Abstract: An electronic device may have a display with an array of inorganic light-emitting diodes. The array of inorganic light-emitting diodes may be overlapped by a polarizer layer such as a circular polarizer. Alternatively, the display may be a polarizer-free display without any polarizer layer over the array of inorganic light-emitting diodes. Each inorganic light-emitting diode may be surrounded by a diffuser that redirects edge-emissions towards a viewer. A top diffuser, a color filter layer, a microlens, and/or a microlens with color filtering and/or diffusive properties may also optionally overlap each inorganic light-emitting diode. The inorganic light-emitting diodes may have reflective sidewalls to mitigate edge-emissions. In this type of arrangement, the array of inorganic light-emitting diodes may be coplanar with one or more opaque masking layers. To mitigate reflections, the display may include two opaque masking layers having differing properties or a single phase separated opaque masking layer.

Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: An extrusion device and a 3D printer are provided. The extrusion device includes a feeding mechanism, a discharging mechanism, a first driving mechanism, a switching mechanism and a second driving mechanism. The feeding mechanism includes a first feeding pipe and a second feeding pipe. The discharging mechanism includes a discharging pipe, and the discharging pipe is connected to the first feeding pipe and the second feeding pipe. The first driving mechanism is used for driving a consumable in the first feeding pipe or the second feeding pipe to move. The switching mechanism corresponds to the first feeding pipe and the second feeding pipe, and the second driving mechanism corresponds to the switching mechanism and is used for driving the switching mechanism to switch between a first state and a second state. The working efficiency of the apparatus can be improved.

Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

Abstract: The present invention discloses a smart clothing and its device mount, wherein the device mount includes an upper casing and a lower casing, a circuit board is arranged between the upper casing and the lower casing, and a metal contact of the top surface of the circuit board penetrates through the upper casing to form a plurality of metal contact points, and the cable interface of the bottom surface of the circuit board passes through the lower casing, and the bottom surface of the lower casing is formed with individual cable grooves toward each cable interface for guiding the transmission wire to insert into the cable interface along the cable groove, and the device mount is combined with a soft gasket on the clothing body and is equipped with a waterproof protective layer to avoid damage to the circuit components and transmission wire during cleaning; when the device mount is installed with the electronic device, the motion status can be monitored.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.

Abstract: A resistive memory device includes an ultrathin barrier layer disposed between the bottom electrode and the bottom electric contact to the memory device. The ultrathin barrier layer may reduce the overall step height of the resistive memory elements by 15% or more, including up to about 20% or more. The use of an ultrathin barrier layer may additionally improve the uniformity of the thickness of the dielectric etch stop layer that partially underlies and extends between the memory elements by at least about 15%. The use of an ultrathin barrier layer may result in improved manufacturability and provide reduced costs and higher yields for resistive memory devices, and may facilitate integration of resistive memory devices in advanced technology nodes.

Abstract: An antenna with multi frequency ranges for communication in more bandwidths includes a dielectric substrate, a first subantenna, a second subantenna, a third subantenna, and first, second, and third isolators. The first to third subantennas are connected to the dielectric substrate and connect with signal sources. The first to third isolators are connected to the dielectric substrate and arranged to be between the first to third subantennas, to improve signal isolation between the subantennas. The application also provides an electronic device with the antenna having multiple frequency ranges. The antenna and the electronic device with the antenna enjoys reduced cross-interference between signals of the first subantenna, the second subantenna, and the third subantenna. The disclosure also provides an electronic device with the antenna.

Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

Abstract: An encoder encodes a video, and includes: circuitry; and memory coupled to the circuitry. Using the memory, the circuitry: obtains at least two items of prediction information for a first partition included in the video; derives at least one template from neighboring samples which neighbor the first partition; calculates at least two costs, using the at least one template and the at least two items of prediction information; using the at least two costs, (i) determines at least one splitting direction for the first partition or (ii) assigns one of the at least two items of prediction information to a second partition split from the first partition according to the splitting direction, and another thereof to a third partition split from the first partition according to the splitting direction; and encodes the first partition according to the splitting direction and the at least two items of prediction information.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

Abstract: Provided herein are compounds, pharmaceutical compositions comprising such compounds, and methods of using such compounds to treat diseases or disorders associated with TRPC3 activity.

Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Abstract: Embodiments of this application provide a display module, an electronic device, and an electronic device control method, and relate to the field of display technologies. Therefore, a pressure sensor can be integrated into a layered structure of the display module, to improve integrity and reliability of a product. The display module includes an active area and an inactive area. The inactive area includes the pressure sensor. The pressure sensor includes one or more pressure sensitive resistors, at least one pressure sensitive resistor is disposed at a same layer as a semiconductor active layer of the active area, and the at least one pressure sensitive resistor is made of a same material as the semiconductor active layer.

Abstract: A manufacturing method of a porous carbon composite material includes the following steps. A polymer template is provided, the polymer template includes a polymer compound, and the polymer template has a plurality of pores. A coating step is performed, wherein a metal compound is coated on the polymer template to form a transition intermediate. A heating step is performed, wherein the transition intermediate is heated to transform the polymer template to a carbon template and transform the metal compound to a coating layer, and a porous carbon composite material is obtained.

Abstract: A manufacturing method of a porous carbon material includes the following steps. A polymer template is provided, the polymer template includes a polymer compound, and the polymer template has a plurality of pores. A coating step is performed, wherein a metal compound is coated on the polymer template to form a transition intermediate. A heating step is performed, wherein the transition intermediate is heated to transform the polymer template to a carbon template and transform the metal compound to a coating layer, and a porous carbon composite material is formed. A removing step is performed, wherein the coating layer is removed from the porous carbon composite material, and a porous carbon material is obtained.