Abstract: Examples pertaining to improvement on user equipment (UE) uplink latency in wireless communications are described. When an apparatus is in a special mode, a processor of the apparatus transmits to a network a request for permission to perform an uplink (UL) transmission for a plurality of times. The processor then receives from the network a grant. In response to receiving the grant, the processor performs the UL transmission to the network. In transmitting the request for the plurality of times, the processor transmits the request for the plurality of times at a frequency higher than a frequency at which the request to perform UL transmissions is transmitted to the network when the apparatus is in a normal operational mode.

Abstract: This invention provides an earphone with a low light transmittance and a non-porous sensor cover. Covering the sensing cover on the proximity sensing device can reduce the interference of most of the ambient light and improve measurement accuracy.

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.

Abstract: A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.

Abstract: An adjustment method of sound output is disclosed. The adjustment method includes the following steps of: receiving an audio message having a vowel message; determining whether the audio message is a whispered voice message; if the audio message is a whispered voice message, outputting a normal voice message, wherein the spoken content of the normal voice message is the same as that of the audio message, and the normal voice message has a normal voice vowel message, wherein the sound energy of the low-frequency part of the normal voice vowel message is 1.5-1,000,000 times that of the vowel message.

Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

Abstract: An optoelectronic device includes a carrier, an electronic component, a photonic component and a supportive component. The electronic component is electrically coupled to the carrier. The photonic component is electrically coupled to the electronic component. The supportive component is disposed outside the photonic component and the electronic component and configured to support an optical component.

Abstract: A heating device is provided. The heating device includes a substrate, a thin-film transistor disposed on the substrate, a heater disposed on the substrate, and a bridging component. The thin-film transistor includes a gate, a semiconductor layer, a source, and a drain. The bridging component is electrically connected to the heater and either the source or the drain. A method for fabricating the heating device is also provided.

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor coupled in series with an isolation transistor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations. During a data refresh, the isolation transistor can be turned on to provide current boosting. During emission periods, the isolation transistor is turned off to prevent cathode noise from potentially coupling through to one or more direct-current voltage nodes in the pixel.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A method includes generating a plurality of vectors representing words in a plurality of documents about an information technology (IT) system and clustering the plurality of vectors to produce a plurality of clusters. The method also includes identifying a cluster of the plurality of clusters that contains a plurality of clustered vectors, generating a feature based on a plurality of words represented by the plurality of clustered vectors, and training a machine learning model to identify an anomaly in the IT system based on the feature.

Abstract: Provided is a method for testing a perovskite precursor solution, including: taking a perovskite precursor solution containing a plurality of dispersed perovskite colloids as a sample to perform liquid analysis, thereby obtaining an analysis information; and determining whether the perovskite precursor solution is a good product based on obtained analysis information from the liquid analysis, wherein the analysis information is at least one selected from the group consisting of element content of the colloid, element distribution, colloid size, and colloid appearance, thereby a feasible and effective testing method is defined through the correlation between the perovskite precursor colloid and the perovskite.

Abstract: A method for driving a touch panel includes applying a touch driving signal to the touch panel for touch sensing, wherein an amplitude of the touch driving signal rises and falls gradually.

Abstract: A method of manufacturing a transistor structure includes forming a plurality of trenches in a substrate, lining the plurality of trenches with a dielectric material, forming first and second substrate regions at opposite sides of the plurality of trenches, and filling the plurality of trenches with a conductive material. The plurality of trenches includes first and second trenches aligned between the first and second substrate regions, and filling the plurality of trenches with the conductive material includes the conductive material extending continuously between the first and second trenches.

Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.

Abstract: A paper feeding mechanism includes a feeding path, a driving motor, a bidirectional transmission mechanism, at least one feeding roller, a unidirectional transmission mechanism and at least one blocking roller. The driving motor is controllable to output a driving force towards a forward direction or a driving force towards a reverse direction. The bidirectional transmission mechanism is connected to the driving motor. The at least one feeding roller is mounted in the feeding path. The at least one feeding roller is connected to the bidirectional transmission mechanism. The unidirectional transmission mechanism is connected to the driving motor. The at least one blocking roller is mounted in the feeding path. The at least one blocking roller is disposed to a downstream of the at least one feeding roller. The at least one blocking roller is connected to the unidirectional transmission mechanism.

Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.