Abstract: A laptop computer including a casing, an inner frame, and a plurality of electronic modules is provided. The inner frame is detachably assembled to the casing and forms a plurality of receiving zones separated from each other. The electronic modules are respectively disposed in the receiving zones and connected to each other via a plurality of flexible electrical conducting members, and the electrical conducting members pass through a recess structure of the inner frame.

Abstract: An intrusion detection method includes steps of obtaining a current detection box and a historical detection box of a target in an input image; determining whether the current detection box has an intersection with a security line or a security area; determining that the target has an intrusion behavior if the current detection box has the intersection with the security line or the security area; and determining a direction of intrusion of the target according to the current detection box and the historical detection box.

Abstract: A fibroblast activation protein (FAP) compound or salt is provided with albumin dual-binding function. It is a new target FAP molecule, comprising a payload group, a linker group and a FAP binding group. The linker group has an architecture selected from four architectures to connect to the payload group and the FAP binding group to form the FAP compound. The target FAP molecule has the biological activity of binding to albumin in blood and that of binding to FAP protein. The present invention is combined with radioactive nuclide Lu-177, Ac-225, Ga-67 or In-111 for long-circulation FAP targeting in the body. Higher accumulation in expressing FAP tumors is achieved, and the accumulation time of inhibitors in tumors is prolonged. The present invention allows radioactivity to act in the tumor for a long time, thereby reducing the radioactivity concentration or reducing the frequency of radioactive inhibitor administration to inhibit tumor growth.

Abstract: A cooling system assembly may include a housing and two pump assemblies. The housing includes two pump cavities, each, disposed parallel against each other, and an inlet and outlet. Each two pump cavities includes a pump cavity inlet and pump cavity outlet. Each two pump assemblies is disposed in each two pump cavities and includes an impeller casing and a liquid driving assembly. Each liquid driving assembly includes a power source and an impeller. Each impeller casing includes a driving chamber, driving chamber inlet, and driving chamber outlet. Each power source respectively drives each impeller to rotate relative to each driving chamber. Each impeller casing defines an inlet chamber separate from the driving chamber. Each driving chamber is fluidly connected to the inlet via each driving chamber inlet, each inlet chamber, and each pump cavity inlet. The outlet is fluidly connected to each driving chamber.

Abstract: A laptop computer including a first casing, a first sub-circuit board, an input module, a second casing, a motherboard, and a bridge circuit board is provided. The first sub-circuit board is disposed at the first casing. The input module is disposed at the first casing and electrically connected to the first sub-circuit board. The motherboard is disposed at the second casing. The first casing and the second casing are assembled together, such that the first sub-circuit board, the bridge circuit board, and the motherboard are partially overlapped, and the first sub-circuit board is electrically connected to the motherboard via the bridge circuit board.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: This application relates to a method for determining a length of an low-density parity-check (LDPC) code word in a ultra-wideband (UWB) system and a related apparatus. The method includes a communication apparatus that determines a length of an LDPC code based on a length of a to-be-encoded information bit. When the length of the information bit ranges from 0 to 324, a 648-bit LDPC code is selected. When the length of the information bit ranges from 325 to 648 or from 973 to 1296, a 1296-bit LDPC code is selected. When the length of the information bit ranges from 649 to 972, a 1944-bit LDPC code is selected. According to embodiments of this application, higher performance gain can be achieved.

Abstract: The present invention provides a circuit structure and a card-shape device comprising the same. The card-shape device includes a first plate, a second plate, a frame and the circuit structure. The frame is disposed between the first plate and the second plate. An accommodating space is defined by the first plate, the second plate and the frame. The circuit structure is disposed in the accommodating space. The circuit structure includes a flexible printed circuit and an interface element. The flexible printed circuit has a first recess and first electrical contacts disposed around the first recess. The interface element has a body, an interface disposed on the body and second electrical contacts disposed on the body and electrically connected with the interface. The interface of the interface element is exposed to the first recess of the flexible printed circuit when the first electrical contacts electrically connect to the second electrical contacts.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: Methods and devices are disclosed for transmitting data, including segmenting a group of information bits into a set of information blocks that each include a respective plurality of the information bits; encoding, using low density parity check (LDPC) encoding, each of the information blocks to generate corresponding codewords; transmitting the codewords to a destination station; receiving a feedback message indicating that at least one of the codewords has not been successfully decoded by the destination station; interleaving the information bits of the information block that corresponds to the at least one of the codewords; encoding, using low density parity check (LDPC) encoding, the interleaved information bits to generate an interleaved codeword; and transmitting the interleaved codeword to the destination station.

Abstract: An encoding method, a decoding method, and an apparatus are provided. The methods include: A transmit end obtains a first bit sequence, performs LDPC encoding based on the first bit sequence to obtain a second bit sequence, and sends the second bit sequence. The first bit sequence includes K0 information bits, sparsity of the first bit sequence is first sparsity, the second bit sequence includes K1 information bits and N1 parity bits, a value of K1 is determined based on the first sparsity, K1 is less than K0, and K1 is a nonnegative integer. Correspondingly, a receive end obtains the second bit sequence, and then performs LDPC decoding on the second bit sequence based on the first sparsity and a code rate, to obtain the K0 information bits.

Abstract: A method includes performing low-density parity-check (LDPC) encoding on a first bit sequence based on a parity check matrix to obtain a first data packet and sending the first data packet. The parity check matrix includes a first parity check matrix and a second parity check matrix, both the first parity check matrix and the second parity check matrix conform to a first base matrix, and a code length of the first parity check matrix is different from a code length of the second parity check matrix.

Abstract: An optical sensing device including a substrate, a light-sensing element, a light-shielding layer, an insulating layer and a light-collecting element is disclosed. The light-sensing element is disposed on the substrate. The light-shielding layer is disposed on the light-sensing element and includes a first opening overlapping the light-sensing element. The insulating layer is disposed on the light-shielding layer and includes a second opening overlapping the first opening. The light-collecting element is disposed on the insulating layer and overlaps the second opening and includes a focus distance F and a first refractive index N1. A second refractive index N3 of an external medium, the first refractive index N1, the focus distance F, and a radius R? of curvature of the light-collecting element meet the following equation: N1/N3=F/(F?R?).

Abstract: A server comprising a circuitry, wherein the circuitry is configured to perform: generating a virtual chatbot via a machine learning model; determining an emotion of the virtual chatbot; feeding information of the emotion into the machine learning model; and setting the virtual chatbot in a live streaming room. According to the present disclosure, the communication between the viewers and AI V-Liver may be improved. Moreover, the quality of the live streaming platform with AI V-Livers may also be improved. Therefore, the user experience may also be improved.

Abstract: A memory operation method, a memory storage device, and a memory control circuit unit are disclosed. The memory operation includes following steps. First data is received from a host system. The first data is stored into a first physical unit which is mapped to a first logical unit. In a first operation mode, a target calculation is performed based on the first data and second data stored in a second physical unit to obtain third data, and the third data is different from the first data. The third data is stored into a third physical unit which is also mapped to the first logical unit. The third data is transmitted to the host system.

Abstract: A method for screening host cells expressing a target protein is provided. The method includes the following steps: providing an expression vector, the expression vector including a promoter, a gene encoding a target protein and an FTH1 gene; transfecting the host cells with the expression vector; culturing the host cells in a medium; and adding iron ions to the medium, and screening the surviving host cells to obtain the host cells expressing the target protein. An expression vector and a method for establishing a cell line stably expressing an exogenous recombinant gene are also provided.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels, that include hybrid thin-film transistor structures formed using semiconducting-oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. A drive transistor in the display pixel may be a top-gate semiconducting-oxide thin-film transistor and a switching transistor in the display pixel may be a top-gate silicon thin-film transistor. A storage capacitor in the display may include a conductive semiconducting-oxide electrode.