Patents by Inventor Wei Ming

Wei Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230088288
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 23, 2023
    Inventors: Yi-Hsiu Liu, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen
  • Publication number: 20230086375
    Abstract: A cam transmission mechanism includes a rotary disk, a camshaft, contact members and a housing. The rotary disk has a periphery formed with equidistant projections, any two adjacent ones of which define an accommodating recess. The camshaft includes a shaft rod and a cam body that has at least one groove communicated with some of the recesses of the rotary disk. The groove and the recesses cooperate to form a plurality of confining spaces, within which the contact members are accommodated freely rollably for rotation transfer from the camshaft to the rotary disk. The housing is connected to the rotary disk for confining the contact members in the confining spaces, respectively.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 23, 2023
    Inventors: Der-Min TSAY, Kun-Lung HSU, Wei-Ming CHEN
  • Patent number: 11610982
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
  • Patent number: 11609901
    Abstract: Techniques are provided for processing a database command in a sharded database. The processing of the database command may include generating or otherwise accessing a shard key expression, and evaluating the shard key expression to identify one or more target shards that contain data used to execute the database command.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: March 21, 2023
    Assignee: Oracle International Corporation
    Inventors: Lik Wong, Leonid Novak, Douglas N. Surber, Ilesh Garish, Saurabh Verma, Wei Ming Hu, Mark Dilman, Jean de Lavarene
  • Publication number: 20230082041
    Abstract: A window blind includes a headrail, a controller, a rotating rod, a pivoting member, a blind body, a bottom rail, two lift cord sets, two tilt cord sets and two cord winding assemblies. With the technical feature that the rotating rod and the tilt members of the cord winding assemblies are arranged in the same axial direction in sequence, the effect of almost synchronous rotation can be achieved, thereby optimizing the complexity of the overall blind window components or related parts.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 16, 2023
    Applicant: CHING FENG HOME FASHIONS CO., LTD.
    Inventors: CHIEN-CHIH HUANG, WEI-MING SHIH
  • Publication number: 20230084821
    Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 16, 2023
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230082084
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 16, 2023
    Inventors: JI CUI, FU-MING HUANG, TING-KUI CHANG, TANG-KUEI CHANG, CHUN-CHIEH LIN, WEI-WEI LIANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUNG YEN, TING-HSUN CHANG, CHI-HSIANG SHEN, LI-CHIEH WU, CHI-JEN LIU
  • Patent number: 11606038
    Abstract: A power converter and control circuit are provided. The control circuit has a power controller for turning on the power switch to maintain a desired output voltage and mode selection switch provides a mode selection signal. Depending on the magnitude of an input voltage of the power converter, in which the mode selection circuit compares the input voltage of the power converter with a reference voltage, a modulation controller is configured to turn on a modulation switch to activate the capacitor according to the mode selection signal.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: March 14, 2023
    Assignee: Diodes Incorporated
    Inventors: Wei Chuan Su, Feng-Jung Huang, Yuan-Hung Lo, Hao-Ming Chen
  • Patent number: 11604403
    Abstract: An imaging system, including a light valve and a projection lens, is provided. The projection lens has a reduction side and a magnification side, and includes a lens group and a convex mirror. The light valve is configured on the reduction side. The projection lens is configured to image the beam from the light valve on a projection surface, and the projection surface is configured on the magnification side. There is an included angle between the projection surface and a light receiving surface. The lens group is configured on an optical path between the magnification side and the reduction side, and includes first to seventh lens elements sequentially arranged from the magnification side to the reduction side. The refractive powers of the first to seventh lens elements are respectively negative, negative, positive, positive, negative, positive, and positive. The convex mirror is configured on an optical path between the lens group and the magnification side.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 14, 2023
    Assignee: Coretronic Corporation
    Inventors: Wei-Ting Wu, Hsin-Hsiang Lo, Ching-Chuan Wei, Chuan-Chung Chang, Fu-Ming Chuang
  • Patent number: 11601050
    Abstract: A voltage regulation system is provided. In the voltage regulation system, a frequency of a clock signal is adjusted and a pulse generator is controlled to output a pulse signal to a switch power stage circuit, to enable the switch power stage circuit to adjust an output voltage and output the adjusted output voltage to the load element. Through the aforementioned configuration, the switch power stage circuit adjusts the output voltage according to the situation of the load element, thus decreasing the power loss of the switch power stage circuit.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 7, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chung-Ming Hsieh, Wei-Chan Hsu
  • Patent number: 11600749
    Abstract: Disclosed is a light-emitting device comprising a light-emitting stack having a length, a width, a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are stacked in a stacking direction. A first electrode is coupled to the first semiconductor layer and extended in a direction parallel to the stacking direction and a second electrode is coupled to the second semiconductor layer and extended in a direction parallel to the stacking direction. A dielectric layer is disposed between the first electrode and the second electrode.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 7, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-I Chen, Wei-Yu Chen, Yi-Ming Chen, Ching-Pei Lin, Tsung-Xian Lee
  • Patent number: 11596145
    Abstract: Disclosed are an anti-freezing agent for protecting a biological tissue from being damaged during a freezing treatment and a preparation method therefor. The method for preparing the anti-freezing agent involves mixing ethylene glycol, water and dimethylsulfoxide homogeneously to form a matrix, and then slowly adding sodium polyacrylate. The prepared anti-freezing agent is coated onto biological tissue during a freezing treatment such that damage to the biological tissue is reduced.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 7, 2023
    Assignee: TAIPEI VETERANS GENERAL HOSPITAL
    Inventors: Po Kuei Wu, Wei Ming Chen, Cheng Fong Chen, Jir You Wang, Wen Hai Wu
  • Patent number: 11600746
    Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: March 7, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Chia-Ming Liu, Chang-Hua Hsieh, Yung-Chung Pan, Chang-Yu Tsai, Ching-Chung Hu, Ming-Pao Chen, Chi Shen, Wei-Chieh Lien
  • Patent number: 11601147
    Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: March 7, 2023
    Assignee: MEDIATEK INC.
    Inventors: Jui-Lin Hsu, Hsiang-Yun Chu, Yen-Tso Chen, Jen-Hao Cheng, Wei-Hsiu Hsu, Tzu-Chin Lin, Chih-Ming Hung, Jing-Hong Conan Zhan
  • Patent number: 11598938
    Abstract: The present disclosure provides an image capturing optical system comprising: a positive first lens element having a convex object-side surface; a negative second lens element having a concave object-side surface; a third lens element; a fourth lens element having a convex object-side surface and a concave image-side surface, the object-side surface and the image-side surface thereof being aspheric; a fifth lens element having a concave image-side surface concave, both of the object-side surface and the image-side surface being aspheric, at least one of the object-side surface and the image-side surface having at least one convex shape in an off-axis region thereof.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: March 7, 2023
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ming Chen, Wei-Yu Chen
  • Patent number: 11598837
    Abstract: Systems and methods for determining a location of a mobile computing device requesting emergency services are provided. A mobile computing device may receive an indication of a request for emergency services from a user of the mobile computing device. The mobile computing device may receive a first wireless signal from a first device. The wireless signal may include an indication of a first geographic position associated with the first device. The mobile computing device may determine a location associated with the mobile computing device based on the indication of the first geographic position associated with the first device, and may send the determined location to a provider of emergency services.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: March 7, 2023
    Assignee: T-MOBILE USA, INC.
    Inventor: Wei-Ming Lan
  • Publication number: 20230067804
    Abstract: A plurality of first semiconductor layers and second semiconductor layers are formed over a front side of a substrate. The first semiconductor layers interleave with the second semiconductor layers in a vertical direction. The first semiconductor layers and second semiconductor layers are etched into a plurality of stacks. The etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view. The bottommost first semiconductor layer is replaced with a dielectric layer. The dielectric layer inherits the tapered profile of the bottommost first semiconductor layer. Gate structures are formed over the stacks. The gate structures each extend in a first horizontal direction. A first interconnect structure is formed over the gate structures. A second interconnect structure is formed over a back side of the substrate.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Shu-Wen Shen, Wei-Yang Lee, Yen-Po Lin, Jiun-Ming Kuo, Kuo-Yi Chao, Yuan-Ching Peng
  • Publication number: 20230061857
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members, a second plurality of channel members, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a frontside source contact disposed between the first plurality of channel members and the second plurality of channel members as well as between the first gate structure and the second gate structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Jui-Ping Lin, Kai-Di Tzeng, Chen-Ming Lee, Wei-Yang Lee
  • Publication number: 20230065194
    Abstract: An electromagnetic interference shielding film includes an insulation layer, a first adhesive layer, a porous metal layer and a conductive adhesive layer including a plurality of conductive particles. The first adhesive layer is located between the insulation layer and the porous metal layer, and the porous metal layer is formed on the first adhesive layer, and making the first adhesive layer locate between the porous metal layer and the insulation layer. The conductive adhesive layer is located on the porous metal layer so that the porous metal layer is located between the first adhesive layer and the conductive adhesive layer. The present invention further provides a preparation method thereof.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 2, 2023
    Inventors: Wei-Chih Lee, Chih-Ming Lin, Chia-Hua Ho, Chien-Hui Lee
  • Patent number: 11592466
    Abstract: A probe card device and a self-aligned probe are provided. The self-aligned probe includes a fixing end portion configured to be abutted against a space transformer, a testing end portion configured to detachably abut against a device under test (DUT), a first connection portion connected to the fixing end portion, a second connection portion connected to the testing end portion, and an arced portion that connects the first connection portion and the second connection portion. The fixing end portion and the testing end portion jointly define a reference line passing there-through. The first connection portion has an aligned protrusion, and a maximum distance between the arced portion and the reference line is greater than 75 ?m and is less than 150 ?m.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 28, 2023
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Kai-Chieh Hsieh, Wei-Jhih Su, Hong-Ming Chen, Vel Sankar Ramachandran