Patents by Inventor Wei Ming

Wei Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250252071
    Abstract: An electronic system and an operating method for the electronic system are provided. The electronic system includes a programmable circuit, a memory circuit, a controller, and a switching circuit. The controller provides a first control signal. The switching circuit has a control terminal, a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the programmable circuit. The second terminal is coupled to the memory circuit. The control terminal and the third terminal are coupled to the controller. The switching circuit receives the first control signal through the control terminal to connect the third terminal to the second terminal, so that update data is stored into the memory circuit.
    Type: Application
    Filed: September 26, 2024
    Publication date: August 7, 2025
    Applicant: PEGATRON CORPORATION
    Inventors: Cong-Feng Wei, Wei-Ming Chen, Yu-Shu Yeh
  • Publication number: 20250252244
    Abstract: The present disclosure provides a method and a non-transitory computer readable media for inter-metal dielectric reliability check. The method comprises: receiving an electronic layout, the electronic layout including a first plurality of electrical components in a first layer; determining an internal voltage difference within each electrical component in the first layer based on parasitic effect; generating a simulation voltage value for each electrical component in the first layer based on the internal voltage differences; and tagging a pair of electrical components in the first layer when a first voltage difference between the pair of electrical components exceeds a first voltage threshold. The first voltage difference is determined based on the simulation voltage value of each electrical component.
    Type: Application
    Filed: April 24, 2025
    Publication date: August 7, 2025
    Inventors: HSIEN YU TSENG, WEI-MING CHEN
  • Patent number: 12380528
    Abstract: A watermark embedding method includes the following steps. The input video signal is received by a processing circuit. Grayscale information of a watermark signal is generated by the processing circuit according to a time series data and a predetermined plane. During a dark sate and a bright state in each of a plurality of consecutive periods, phases of the time series data are opposite and integral values of the grayscales of the predetermined plane are the same. The processing circuit embeds the watermark signal into the input video signal to generate an output video signal with the watermark information. The display panel displays an image according to the output video signal.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: August 5, 2025
    Assignee: AUO CORPORATION
    Inventors: Yang-En Wu, Wen-Rei Guo, Wei-Ming Cheng, Chao-Wei Li
  • Patent number: 12380130
    Abstract: A lead-sync log record is used to synchronize the replication logs of follower shards to the leader shard. In response to a failure to determine that there is a consensus for a database transaction commit operation after a shard server becomes a new leader, the new leader shard performs a sync operation using the lead-sync log record to synchronize replication logs of the follower shards to the replication log of the new leader. A shard server identifies a first transaction having a first log record but not a post-commit log record in the replication log, defines a recovery window in the replication log starting at the first log record of the identified first transaction and ending at the lead-sync log record, identifies a set of transactions to be recovered, and performs a recovery action on the set of transactions to be recovered.
    Type: Grant
    Filed: September 22, 2023
    Date of Patent: August 5, 2025
    Assignee: Oracle International Corporation
    Inventors: Lik Wong, Leonid Novak, Sampanna Salunke, Mark Dilman, Wei-Ming Hu
  • Patent number: 12374596
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai
  • Patent number: 12374602
    Abstract: A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Yu-Hsiao Lin, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20250239499
    Abstract: An ultra-thin packaged component and its manufacturing method are provided. The packaged component includes a die, at least one conductive component, an encapsulant layer, and multiple conductive contacts. The encapsulant layer surrounds and covers the die and the conductive component, with multiple conductive contacts placed on the surface of the encapsulant layer that electrically connect the die and the conductive component. During the manufacturing of the packaged component, the die and the conductive component are first encapsulated with the encapsulant layer and then simultaneously thinned through grinding. Such process protects the die with the encapsulant layer to prevent cracking and reduces the thickness of the base layer of the die closer to that of its epitaxy layer, achieving the objective of thinness.
    Type: Application
    Filed: July 5, 2024
    Publication date: July 24, 2025
    Inventors: CHUNG-HSIUNG HO, CHIEN-CHUN WANG, CHI-HSUEH LI, WEI-MING HUNG, JENG-SIAN WU
  • Patent number: 12368577
    Abstract: A method for managing a digital identity system includes generating a user digital identity for a user, generating an asset digital identity for an asset, generating a user public key and a user private key after the user digital identity is generated, generating descriptive data related to the asset, generating a data public key and a data private key after the descriptive data is generated, encrypting the data with the data public key to generate encrypted data, saving the data private key on a user end, uploading the encrypted data to a cloud database, a platform reading the encrypted data from the cloud database, a data requester querying and requesting for data, forwarding a data request to a data owner in an qualified data owner set and granting a data access to the data request if the data owner accepts the data request.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: July 22, 2025
    Assignee: LSC Ecosystem Corporation
    Inventors: Wei-Ming Li, Kuan-Hsun Cho, Sung-Ching Lin
  • Publication number: 20250231221
    Abstract: A voltage measurement device with an expanded applicability is provided. The voltage measurement device includes a housing, a magnetic member, a first probe assembly, and a second probe assembly. By setting the magnetic member within the housing, the voltage measurement device can be magnetically attracted to any position on the busbar of the device to be measured. Additionally, the second probe assembly is movable, enabling voltage measurements on busbars of different thicknesses and devices of different sizes, expanding the applicability of the voltage measurement device.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 17, 2025
    Inventors: Wei-Ming Lee, Chi-Wen Chen
  • Patent number: 12354267
    Abstract: The present disclosure generally relates to systems and methods for evaluating viability of oocytes. In some implementation examples, an image sequence associated with an oocyte being aspirated into a pressure tool is obtained. Using a segmentation model, objects associated with the oocyte can be identified. Based on the objects identified, features such as morphological features and an aspiration depth associated with the oocyte can be determined. At least some of the features can then be fed into a machine learning model to generate an oocyte grade that indicates a likelihood of the oocyte developing into a usable blastocyst. Optionally, the oocyte grade can be presented to a user via an interactive user interface.
    Type: Grant
    Filed: October 2, 2024
    Date of Patent: July 8, 2025
    Assignee: Inti Taiwan, Inc.
    Inventors: Wei-Ming Chen, I-Chiao Hsieh, Chung-Li Chiang
  • Publication number: 20250218369
    Abstract: A display driving device comprises a signal supplier and a panel. The signal supplier is configured to output a first data signal, a second data signal, and a third data signal. The panel is coupled to the signal supplier. The panel includes a first region to a ninth region. During a first period, the first region, the second region, and the third region output a red signal based on the first data signal, the fourth region, the fifth region, and the sixth region output a green signal based on the second data signal, and the seventh region, the eighth region and the ninth region output a blue signal based on the third data signal. The red signal, the green signal, and the blue signal are different from each other.
    Type: Application
    Filed: October 30, 2024
    Publication date: July 3, 2025
    Inventors: Cheng-Kuang WANG, Syuan-Ying LIN, Min-Hsuan CHIU, Wei-Ming CHENG, Chen-Yu CHANG, Shu-Hao HUANG, Ya-Jung WANG, Ting-Wei GUO, Sung-Yu SU
  • Publication number: 20250191522
    Abstract: A display driving device includes a panel. The panel includes an output region, a first region, a second region, and a third region. The output region is configured to output a detection signal. The first region overlaps the output region, the second region overlaps the output region, and the third region overlaps the output region. During a first period, the second region and the third region output a point report signal according to the detection signal. During a second period, the first region and the third region output the point report signal according to the detection signal. During a third period, the first region and the second region output the point report signal according to the detection signal. The second period is later than the first period and the third period is later than the second period.
    Type: Application
    Filed: June 21, 2024
    Publication date: June 12, 2025
    Inventors: Ya-Jung WANG, Yu-Feng Chien, Ting-Wei Guo, Shu-Hao Huang, Min-Hsuan Chiu, Syuan-Ying Lin, Cheng-Kuang Wang, Chen-Yu Chang, Wei-Ming Cheng, Sung-Yu Su
  • Publication number: 20250191527
    Abstract: A display panel includes a pixel circuit. The pixel circuit includes a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit includes a first light emitting element and a first driving circuit. The first driving circuit is coupled to the first light emitting element, and is configured to conduct according to a first driving signal and a second driving signal to drive the first light emitting element. The second sub-pixel circuit includes a second light emitting element, a third light emitting element and a second driving circuit. The second driving circuit is coupled to the second light emitting element and the third light emitting element, is configured to conduct according to the first driving signal to drive the second light emitting element, and is configured to conduct according to the second driving signal to drive the third light emitting element.
    Type: Application
    Filed: October 30, 2024
    Publication date: June 12, 2025
    Inventors: Syuan-Ying LIN, Cheng-Kuang WANG, Min-Hsuan CHIU, Wei-Ming CHENG, Ya-Jung WANG, Ting-Wei GUO, Shu-Hao HUANG, Sung-Yu SU
  • Publication number: 20250184276
    Abstract: A traffic patterned-based modem function adjustment method includes receiving at least one traffic pattern by a user device, identifying the at least one traffic pattern by the user device for detecting a traffic mode of the user device, acquiring assisted information of the at least one traffic pattern by the user device, and adjusting at least one modem function according to the traffic mode and the assisted information. The at least one traffic pattern includes packet transmission characteristics, a radio signal status, and/or codec information of a network communicating with the user device.
    Type: Application
    Filed: December 1, 2024
    Publication date: June 5, 2025
    Applicant: MEDIATEK INC.
    Inventors: Wei-Ming Yin, Pei-Tsung Wu, Yi-Ting Cheng, Wan-Ting Huang, Tsung-Ting Chiang, Tsung-Ming Lee, Chih-Chuan Cheng, Kun-Lin Wu, Chien-Li Chou, Shang-An Tsai, Hung-Lin Chang, Chung-Pi Lee
  • Publication number: 20250176267
    Abstract: A pixel structure includes a first conductive pattern layer, a voltage line bridge structure, and a second conductive pattern layer. The first conductive pattern layer includes a first light-emitting signal line and a voltage line. The first light-emitting signal line extends in a first direction. The voltage line includes a first voltage line segment and a second voltage line segment located on both sides of the first light-emitting signal line and separated from each other. The first voltage line segment and the second voltage line segment extend in a second direction. The voltage line bridge structure electrically connects the first voltage line segment to the second voltage line segment. The second conductive pattern layer includes a scan line and a first data line. The scan line extends in the first direction. The first data line extends in the second direction and at least partially overlaps the voltage line.
    Type: Application
    Filed: September 26, 2024
    Publication date: May 29, 2025
    Applicant: AUO Corporation
    Inventors: Syuan-Ying Lin, Cheng-Kuang Wang, Min-Hsuan Chiu, Wei-Ming Cheng
  • Publication number: 20250174586
    Abstract: A semiconductor structure includes a substrate, a bonding structure disposed over the substrate, and a filling layer. The substrate includes an optically active region and an optical surface in the optically active region. The bonding structure includes a bonding dielectric layer and conductive features in the bonding dielectric layer and arranged outside a keep-out zone of the bonding structure, where in a first view, the keep-out zone is located in the optically active region, and a first feature of the conductive features is disposed between the optically active region and the keep-out zone. The filling layer is interposed between the bonding structure and the optically active region of the substrate. The first feature is separated from the filling layer by the bonding dielectric layer in a second view.
    Type: Application
    Filed: November 26, 2023
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hui Lin, Chen Chen, Chih-Hao Yu, Wei-Ming Wang, Ren-Fen Tsui, Chen-Hua Yu
  • Publication number: 20250174574
    Abstract: Chip packages are provided. The chip package includes a device substrate, at least one signal/power pad, and a patterned metal plate. The device substrate has an active surface and a backside surface. The device substrate includes a first opening and a second opening that extend from the backside surface through the device substrate to the active surface. The signal/power pad is disposed on the backside surface of the device substrate. The patterned metal plate is disposed on the backside surface, and it surrounds and is separated from the signal/power pad. The patterned metal plate includes a plurality of first slit openings exposing the backside surface, extending along a first direction and arranged parallel to each other.
    Type: Application
    Filed: November 8, 2024
    Publication date: May 29, 2025
    Inventors: Wei-Ming CHIEN, Po-Han LEE, Yi-Jui HOU
  • Patent number: 12317750
    Abstract: Disclosed herein is a buckling actuator, comprising: a first electrode; a second electrode; and a film of a dielectric elastomeric material having a first surface and a second surface sandwiched between the first and second electrodes, wherein the material is formed by the random block copolymerisation of a polymeric material comprising silicon or nitrogen atoms that has two or more acrylate or vinyl end groups, and a polar polymeric material having two or more acrylate or vinyl end groups. Also disclosed herein is a method of forming said dielectric elastomeric material.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: May 27, 2025
    Assignee: Nanyang Technological University
    Inventors: Wei Ming Matthew Tan, Gurunathan Thangavel, Pooi See Lee
  • Patent number: 12314652
    Abstract: The present disclosure provides a method and a non-transitory computer readable media for inter-metal dielectric reliability check. The method comprises: receiving an electronic layout, the electronic layout including a first plurality of electrical components in a first layer; determining an internal voltage difference within each electrical component in the first layer based on parasitic effect; generating a simulation voltage value for each electrical component in the first layer based on the internal voltage differences; and tagging a pair of electrical components in the first layer when a first voltage difference between the pair of electrical components exceeds a first voltage threshold. The first voltage difference is determined based on the simulation voltage value of each electrical component.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien Yu Tseng, Wei-Ming Chen
  • Publication number: 20250157553
    Abstract: A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.
    Type: Application
    Filed: September 11, 2024
    Publication date: May 15, 2025
    Applicant: eMemory Technology Inc.
    Inventors: Wei-Ming Ku, Wei-Chiang Ong, Chih-Yang Huang, Che-Wei Chang