Patents by Inventor Wei Ming

Wei Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935825
    Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Cheng-Chi Chuang, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan
  • Publication number: 20240089090
    Abstract: A method for managing a digital identity system includes generating a user digital identity for a user, generating an asset digital identity for an asset, generating a user public key and a user private key after the user digital identity is generated, generating descriptive data related to the asset, generating a data public key and a data private key after the descriptive data is generated, encrypting the data with the data public key to generate encrypted data, saving the data private key on a user end, uploading the encrypted data to a cloud database, a platform reading the encrypted data from the cloud database, a data requester querying and requesting for data, forwarding a data request to a data owner in an qualified data owner set and granting a data access to the data request if the data owner accepts the data request.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 14, 2024
    Applicant: LSC Ecosystem Corporation
    Inventors: Wei-Ming Li, Kuan-Hsun Cho, Sung-Ching Lin
  • Publication number: 20240086503
    Abstract: A computing system receives a request to verify a user, the request comprising an indication of a jurisdiction in which the user will be verified. Based on the request, the computing system collects information related to the user. Based on the request, the computing system identifies a workflow corresponding to the jurisdiction. The workflow defines conditions for obtaining a verified status in the jurisdiction. The computing system executes the workflow to verify the user. The computing system hashes the verification record using a zero-knowledge proof protocol. The computing system generates a non-fungible token corresponding to the verification record. The non-fungible token is associated with a hashed version of the verification record. The computing system broadcasts the non-fungible token to a blockchain.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 14, 2024
    Applicant: HSBC Software Development (Guangdong) Limited
    Inventors: Benjamin Evans Chodroff, Yong Xia, Wei Ming Zhuang, Ying Li Liu
  • Publication number: 20240088155
    Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu LAI, Kai-Hsuan LEE, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Patent number: 11929355
    Abstract: A mixed light light-emitting diode device includes first, second, and third chips, each having a first-type semiconductor layer with a first surface, a second-type semiconductor layer with a second surface opposite to the first surface, and a third surface indenting from the first surface and situated on the second-type semiconductor layer. The second and third chips have their first surfaces disposed above and facing the first surface of the first chip. A first-type electrode penetrates through the second and first surfaces of the first chip and contacts all first surfaces of first, second, and third chips. Two second-type electrodes each penetrates through the second and third surfaces of the first chip and connect the first chip to one of the second and third chips.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: March 12, 2024
    Assignee: MACROBLOCK, INC.
    Inventors: Shih-Sian Liang, Wei-Ming Tseng
  • Publication number: 20240079239
    Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Inventors: Bau-Ming Wang, Liang-Yin Chen, Wei Tse Hsu, Jung-Tsan Tsai, Ya-Ching Tseng, Chunyii Liu
  • Patent number: 11924713
    Abstract: Systems and methods for providing timely location estimates when a user equipment initiates a call to an emergency number are disclosed. The system enables a user equipment to send the earliest available location that the user equipment can come up with, after detecting an emergency message (e.g., detecting a 911 digit string). This can be done by sending the current location of the user equipment via HTTPS protocol to a telecommunications service provider node (e.g., an end point in GMLC). In this manner, the system avoids a major overhaul of the existing 3GPP E911 location standard while allowing timely compliance of the NG911 mandate.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: March 5, 2024
    Assignee: T-Mobile USA, Inc.
    Inventor: Wei-Ming Lan
  • Patent number: 11924342
    Abstract: Improved computer-implemented methods for evidencing the existence of a digital document, anonymously evidencing the existence of a digital document, database management for systems for evidencing the existence of a digital document, and verifying the data integrity of a digital document provide increased reliability, security and enhance trust from users and third parties.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 5, 2024
    Assignee: 707 Limited
    Inventors: Johnson Zone An Kong, Michael Ming-Jae Lin, Wei Hsiung Nicolas Yang
  • Patent number: 11918329
    Abstract: A physiological detection device includes system including a first array PPG detector, a second array PPG detector, a display and a processing unit. The first array PPG detector is configured to generate a plurality of first PPG signals. The second array PPG detector is configured to generate a plurality of second PPG signals. The display is configured to show a detected result of the physiological detection system. The processing unit is configured to convert the plurality of first PPG signals and the plurality of second PPG signals to a first 3D energy distribution and a second 3D energy distribution, respectively, and control the display to show an alert message.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 5, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chiung-Wen Lin, Wei-Ru Han, Yang-Ming Chou, Cheng-Nan Tsai, Ren-Hau Gu, Chih-Yuan Chuang
  • Patent number: 11923205
    Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
  • Publication number: 20240068086
    Abstract: Target assemblies for PVD chambers are provided herein. In some embodiments, a target assembly for a PVD chamber includes: a backing plate; and a target coupled to the backing plate and having a substrate facing surface opposite the backing plate, wherein a peripheral portion of the target includes an angled surface extending radially outward and toward the backing plate, wherein an annular portion of the angled surface has a surface roughness greater than a surface roughness of a remainder of the substrate facing surface of the target.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 29, 2024
    Inventors: Sundarapandian Ramalinga Vijayalakshmi REDDY, Kirankumar Neelasandra SAVANDAIAH, Junqi WEI, Bridger Earl HOERNER, Kelvin Tai Ming BOH, Madan Kumar SHIMOGA MYLARAPPA
  • Patent number: 11917803
    Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11917230
    Abstract: A system and method for maximizing bandwidth in an uplink for a 5G communication system is disclosed. Multiple end devices generate image streams. A gateway is coupled to the end devices. The gateway includes a gateway monitor agent collecting utilization rate data of the gateway and an image inspector collecting inspection data from the received image streams. An edge server is coupled to the gateway. The edge server includes an edge server monitor agent collecting utilization rate data of the edge server. An analytics manager is coupled to the gateway and the edge server. The analytics manager is configured to determine an allocation strategy based on the collected utilization rate data from the gateway and the edge server.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 27, 2024
    Assignee: Quanta Cloud Technology Inc.
    Inventors: Yi-Neng Zeng, Keng-Cheng Liu, Wei-Ming Huang, Shih-Hsun Lai, Ji-Jeng Lin, Chia-Jui Lee, Liao Jin Xiang
  • Patent number: 11917490
    Abstract: Systems, methods, and computer-readable media herein generate an E911 location report based on an uncertainty associated with a device-based hybrid (DBH) location received from a UE device. The uncertainty may be compared to an uncertainty threshold value to determine which values to include in a location report sent to a PSAP. A civic address associated with a UE device may be included in a location report where the uncertainty is sufficiently low, thus a location report can be sent to a PSAP with the most relevant and accurate information so that first responders can more effectively locate a distressed caller.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: February 27, 2024
    Assignee: T-Mobile Innovations LLC
    Inventors: Nan Xiao, Wei-Ming Lan
  • Patent number: 11913472
    Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 11916155
    Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 27, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
  • Publication number: 20240062729
    Abstract: A display device, including a display module, a photodetector, a processor, and an optical structure layer, is provided. The display module is used for displaying an image. The photodetector is electrically connected to the display module and is used for detecting brightness of an ambient light and outputting a sensing signal. The processor is electrically connected to the display module and the photodetector, and is used for receiving the sensing signal and outputting a command signal to the display module according to the sensing signal, so that the display module adjusts brightness of the image according to the command signal. The optical structure layer is disposed on the display module. A glossiness of the optical structure layer is between 4 GU and 35 GU, and a reflectivity of specular component included (SCI) of the optical structure layer is between 3% and 6%.
    Type: Application
    Filed: July 13, 2023
    Publication date: February 22, 2024
    Applicant: Innolux Corporation
    Inventors: Yu-Chun Hsu, Wei-Ming Chu, Sheng-Nan Fan
  • Patent number: 11905168
    Abstract: A manufacturing method of miniature fluid actuator is disclosed and includes the following steps. A flow-channel main body manufactured by a CMOS process is provided, and an actuating unit is formed by a deposition process, a photolithography process and an etching process. Then, at least one flow channel is formed by etching, and a vibration layer and a central through hole are formed by a photolithography process and an etching process. After that, an orifice layer is provided to form at least one outflow opening by an etching process, and then a chamber is formed by rolling a dry film material on the orifice layer. Finally, the orifice layer and the flow-channel main body are flip-chip aligned and hot-pressed, and then the miniature fluid actuator is obtained by a flip-chip alignment process and a hot pressing process.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: February 20, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Hsien-Chung Tai, Lin-Huei Fang, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee
  • Patent number: 11898554
    Abstract: A filtration and purification processing method includes following steps: (1) providing a filtration and purification device; (2) performing a gas introduction, filtration, and detection procedure; (3) performing a detection and determination procedure to the purified gas; (4) performing a circulating filtration and detection procedure to the purified gas; and (5) repeating filtration and purification procedures to the purified gas several times and guiding out the purified gas.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: February 13, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee, Tsung-I Lin, Yang Ku