Abstract: A heat sink module includes a heat dissipation pad. The heat dissipation pad is flexible and has a cambered shape, and is pressed to become a flat plate when disposed between the heat sink module and a CPU. The heat dissipation pad restores to its original cumbered shape and lifts the heat sink module away from a CPU when a fixing device that fixes the heat sink module to the CPU is disabled. Therefore, one can easily removes the heat sink module without any additional tools or processes.

Abstract: A local exhaust system for volatile organic compound (VOC) pollution control comprises a plurality of hoods, pipelines, and airflow regulators. The plurality of hoods at one side of an article and around thereof and air flows at the other side to remove VOC thereon to generate polluted air flow such that the plurality of hoods receives and collects the polluted air. The plurality of pipelines connected to the plurality of hoods is to take the polluted air therefrom. The plurality of airflow regulators on the plurality of pipelines is to adjust air flow therein.

Abstract: An improved method, mechanism, and system for implementing, generating, and maintaining records, such as redo records and redo logs in a database system, are disclosed. Multiple sets of records may be created and combined into a partially ordered (or non-ordered) group of records, which are later collectively ordered or sorted as needed to create an fully ordered set of records. With respect to a database system, redo generation bottleneck is minimized by providing multiple in-memory redo buffers that are available to hold redo records generated by multiple threads of execution. When the in-memory redo buffers are written to a persistent storage medium, no specific ordering needs to be specified with respect to the redo records from the different in-memory redo buffers. While the collective group of records may not be ordered, the written-out redo records may be partially ordered based upon the ordered redo records from within individual in-memory redo buffers.

Abstract: An embedded microelectronic capacitor equipped with geometrically-centered electrodes which includes an upper electrode plate of a first polarity; a middle electrode plate of a second polarity opposite to the first polarity; at least one lower electrode plate of the first polarity in electrical communication with the upper electrode plate through a center via. The center via is positioned at a distance from a geometric center of the middle electrode plate of not larger than 50% of the diameter of the plate, and preferably not larger than 30% of the diameter.

Abstract: Techniques are described herein for returning a repository to a prior state. The repository may be, for example a database, and the prior state may be, for example the consistent state that the database had at a particular point in time in the past. When a operator-caused error has been introduced to the database by changes made by an already-committed transaction, the techniques described herein may be used to recover from the error by returning the database to a point in time prior to the commit time of the transaction that introduced the error. The techniques involve the generation of “physical undo” information, and the use of the physical undo information in conjunction with physiological undo and physiological redo to efficiently return a repository to the prior state.

Abstract: An embedded microelectronic capacitor equipped with geometrically-centered electrodes which includes an upper electrode plate of a first polarity; a middle electrode plate of a second polarity opposite to the first polarity; at least one lower electrode plate of the first polarity in electrical communication with the upper electrode plate through a center via. The center via is positioned at a distance from a geometric center of the middle electrode plate of not larger than 50% of the diameter of the plate, and preferably not larger than 30% of the diameter.

Abstract: A method of forming dual salicides for integrated circuits. A mask layer is formed over a substrate having a first transistor and a second transistor thereon. The top surface of the first transistor's gate is higher than that of the second transistors' gate. The mask layer is patterned to expose the top surface of the second transistor's gate, source and drain. First metal suicides are formed respectively on the top surfaces of the second transistor's gate, source and drain. A dielectric layer is formed over the substrate, and the top surface of the dielectric layer is higher than that of the first transistor's gate. The dielectric layer, higher than the top surface of the second transistor's gate, is removed to expose the top surfaces of the first and the second transistors' gates. A second metal silicide is formed on the top surface of the first transistor's gate.

Abstract: An approach for performing data block location verification includes inserting an address value into a data block that identifies a desired location in nonvolatile memory for storing the data block. Prior to performing an operation that stores the data block to the nonvolatile memory, a determination is made whether the address value in the data block correctly identifies the location in nonvolatile memory into which the operation will store the data block. The operation is performed only if the address value in the data block correctly identifies the location in nonvolatile memory into which the operation will store the data block. After the data block is read from the nonvolatile memory, an additional determination may be made to determine whether the data block was read from the desired location in the nonvolatile memory.

Abstract: The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.

Abstract: A method including operating an ion implanted to implanting ions in a semiconductor wafer at a first ion dose level; performing a first thermal wave measurement to obtain the first thermal wave value; placing the semiconductor wafer in a rapid thermal annealing furnace and operating the furnace to rapidly heat the semiconductor wafer at a first rate for a first time period and so that the wafer is heated with intent of achieving a wafer temperature of 500° C.; performing a second thermal wave measurement to obtain a second thermal wave value; comparing the difference between the first thermal wave value and the second thermal wave value to a target range of 376.5-382.5 and rejecting the wafer as being outside of an acceptable specification if the difference is outside of the target range.

Abstract: To rapidly respond to successive abnormal defect events, a defect alarm system and method comprises counting the defect detection data from a defect scan station using a defect data analysis system and producing a trend chart for the defect detection data. A defect data analysis system analyzes the trend chart at a constant time frame and records the successive abnormal defect events to produce a defect alarm report, and an email system automatically sends out the defect alarm report to notice the responsible engineer timely. After receiving the notice, the engineer compares the received defect distribution map with those of known events in a defect pattern database to judge if the event is a known one to propose a policy.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: A method of optimal contention region allocation for medium access control in multipoint-to-point networks, and in particular a method of obtaining optimal contention region allocation so that to achieve optimal throughput. The method establishes an optimal table so that the object of optimal allocation to reduce collision for medium access in multipoint-to-point networks can be achieved. Based on the aspects of present invention, optimal throughput can be achieved, thus reducing the wastage of bandwidth.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: The present invention discloses a method for manufacturing an array structure in integrated circuits (IC). The method for manufacturing an array structure in integrated circuits of the present invention is performed by using two masks. First, a first mask having array pattern of holes is used to perform a first exposing step with a partial dose, and a second mask having code patterns is used to perform a second exposing step with a compensating dose for the first exposing step, so that a photoresist covering the regions of the holes desired to be opened obtains a sufficient exposure dose and the holes desired are formed by developing. Therefore, a preferred resolution and a preferred depth of focus (DOF) for exposure are obtained, thereby reducing optical proximity effect (OPE), and it is quite easily to manufacture the masks used in the present invention.

Abstract: A method for measuring a dielectric layer thickness calibration reference standard including providing a substrate having a dielectric layer for calibrating a dielectric layer thickness measuring tool; cleaning the dielectric layer according to a cleaning process including at least one of spraying and scrubbing; and, measuring the thickness of the dielectric layer with the dielectric layer thickness measuring tool including at least one portion of the dielectric layer displaced from the substrate center.

Abstract: A wafer container having a latching mechanism utilized to lock the door of the wafer container in an airtight status. The latching mechanism comprises a cam rotated to move a link and a locking plate pivoted to one end of the link, and a guide block adapted to guide the locking plate sliding into an insertion hole in the container body of the wafer container by using a straight guide means and a curved guide means of the guide block and then to turn the locking plate about pivot rods at the link, causing the locking plate to withstand against part of the container body and to hold down the door toward the inside of the container body and to lock the door in an airtight status.

Abstract: A wafer boat including a partition which separates vertically adjacent wafer slots in the wafer boat and at least partially shields each wafer from the backside emissivity of the adjacently overlying wafer in order to form oxide layers of substantially uniform thickness on the wafers during thermal oxidation processing. Each of the partitions may be constructed of quartz. In another embodiment, each wafer is at least partially shielded from the backside emissivity of the adjacently overlying wafer by separating or partitioning the wafers using a bare or uncoated wafer.

Abstract: The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.

Abstract: The invention discloses a signal decoding method for C3 decoding on a data storage medium. The data storage medium contains a lot of sectors, and each sector contains two C3 codes. Each C3 code contains a plurality of P codes and Q codes. The syndrome operation for an (N+1)th code and an error-correction for an N-th code are pipelined. An address for the (N+1)th code minus a predetermined value is an address for the N-th code.