Abstract: A guiding laryngoscope includes a holding part, a bending part and a tongue lifting part. The bending part is connected with an end of the holding part, and a guiding groove for guiding an intubation tube is provided in the bending part. One end of the tongue lifting part is connected with an end of the bending part away from the holding part and faces a side of the holding part, and the other end of the tongue lifting part is arranged to extend along a bending direction of the bending part. A first included angle between an extension line of a tube-out end of the guiding groove and a central axis of the holding part is smaller than a second included angle between an extension line of an end of the tongue lifting part and the central axis of the holding part.

Abstract: A wearable air conditioner includes a shell for being worn around a wearing portion of a user, a fan and a temperature regulating member disposed in the shell. The shell includes a first air passage, a first accommodating chamber, at least one air outlet in communication with the first air passage, and vent holes in communication with the first accommodating chamber. The temperature regulating member is configured for generating heat energy or cold energy. The temperature regulating member is in thermal connection with a sidewall of the first accommodating chamber. An airflow generated by the fan is capable of entering the first air passage and then exiting the shell via the at least air outlet.

Abstract: A method of forming a package comprises forming a stack of chip layers on a carrier. The stack of chip layers including at least a first chip layer over the carrier and a second chip layer over the first chip layer. The first chip layer includes a plurality of first chips facing the carrier and a plurality of chip couplers. The second chip layer includes a plurality of second chips facing the first chip layer. The method further comprises encapsulating the stack of chip layers in a molding compound, removing the carrier to expose the front side of the first chip layer, forming a redistribution layer on the front side of the first chip layer, and dividing the stack of chips and the redistribution layer to form a plurality of the packages. A chip package thus formed includes a stack of chips and one or more chip connectors on a singulated redistribution layer.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-level assembly, including: align and fix at least one first-level device to a target position on a carrier plate by utilizing the self-alignment capability of first-level alignment solder joints; encapsulating the at least one first-level device to form a molded package body; and exposing the first-level interconnect terminals from the molded package body. The packaging method further comprises align and fix a second-level device to a target position on the first-level assembly by utilizing the self-alignment capability of second-stage alignment solder joints between the first-level assembly and the second-level device. The packaging method improves the operation speed and accuracy of the picking and placing of the first-level device and the second-level device, resulting in improved process efficiency and reduced process cost.

Abstract: A method of forming a package comprises assembling at least one chip layer over a carrier substrate, the at least one chip layer including chip couplers and chips, each of the chips having a front side facing the carrier substrate and chip contacts formed on the front side, the couplers including first chip couplers, each of the first chip couplers having an upper side facing away from the carrier substrate and first bumps formed on the upper side. The method further comprises encapsulating the at least one chip layer to form a molded package structure, thinning the molded package structure to expose the first bumps, forming a metal layer on a side of the molded package structure where the first bumps are exposed, removing the carrier to expose another side of the molded package structure, and forming a redistribution layer and second bumps on the molded package structure.

Abstract: Self-mixing interferometry (SMI) sensors may include vertical cavity surface emitting lasers (VCSEL), photodetectors, and microelectromechanical systems (MEMS). The VCSEL, photodetectors, and MEMS may be vertically stacked. The MEMS may be moveable with respect to a VCSEL and may change a cavity length associated with the VCSEL. By changing the cavity length associated with the VCSEL, certain properties of emitted light may be changed, such as a wavelength value of the emitted light.

Abstract: A method of forming a package comprises forming a stack of chip layers on a carrier. The stack of chip layers including at least a first chip layer over the carrier and a second chip layer over the first chip layer. The first chip layer includes a plurality of first chips facing the carrier and a plurality of chip couplers. The second chip layer includes a plurality of second chips facing the first chip layer. The method further comprises encapsulating the stack of chip layers in a molding compound, removing the carrier to expose the front side of the first chip layer, forming a redistribution layer on the front side of the first chip layer and bumps on the redistribution layer, and dividing the stack of chips and the redistribution layer to form a plurality of the packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.

Abstract: The present disclosure provides a method for forming a semiconductor package and a semiconductor package. The method comprises providing a semiconductor wafer with at least one semiconductor device formed thereon, the at least one semiconductor device comprising a plurality of metal bond pads formed on the semiconductor wafer. The method further comprises forming a first photoresist layer having a first opening directly above at least a portion of a first metal bond pad; forming a first metal feature of a first height in the first opening; removing the first photoresist layer; forming a second photoresist layer having a second opening directly above at least a portion of the second metal bond pad; forming a second metal feature of a second height in the second opening; and removing the second photoresist layer. Using the method, metal bumps having different heights and different sizes can be formed in a controlled manner.

Abstract: A method of forming a package is provided. The method comprises assembling on a carrier a stack of chip layers including a plurality of first chip layers and a second chip layer; encapsulating the stack of chip layers in a molding compound; removing the carrier to form a package main body; forming a redistribution layer on an exposed side of a first chip layer; and dividing the package main body to form a plurality of packages. Each first chip layer includes first chips and chip couplers. A chip package includes at least one chip stack and at least one chip coupler stack on a singulated redistribution layer. Each chip stack includes at least one chip from each chip layer, and each chip coupler stack includes at least one chip coupler and/or at least one chip coupler segment from each of the first chip layers.

Abstract: Disclosed herein are self-mixing interferometry (SMI) sensors, such as may include vertical cavity surface emitting laser (VCSEL) diodes and resonance cavity photodetectors (RCPDs). Structures for the VCSEL diodes and RCPDs are disclosed. In some embodiments, a VCSEL diode and an RCPD are laterally adjacent and formed from a common set of semiconductor layers epitaxially formed on a common substrate. In some embodiments, a first and a second VCSEL diode are laterally adjacent and formed from a common set of semiconductor layers epitaxially formed on a common substrate, and an RCPD is formed on the second VCSEL diode. In some embodiments, a VCSEL diode may include two quantum well layers, with a tunnel junction layer between them. In some embodiments, an RCPD may be vertically integrated with a VCSEL diode.

Abstract: Embodiments are directed to electronic devices that include a surface emitting laser array including a first set of light emitters distributed across the surface emitting laser array and configured to emit laser light into an environment of the electronic device. The laser array can also include a second set of light emitters interspersed with the first set of light emitters, where each light emitter in the second set of light emitters includes a first set of layers defining a first mirror, a second set of layers defining a second mirror, and a third set of layers positioned between the first set of layers and the second set of layers and defining a laser cavity. The surface emitting laser array can include a light blocking material positioned on one or more of the second set of light emitters and configured to cause localized heating of the laser array.

Abstract: A portable temperature regulation device defining a wear space, includes a main body, a protrusion portion, and a temperature conducting member at least partly arranged on the protrusion portion. The main body has a first side and a second side. The protrusion portion extends from the first side in a direction away from the second side. In use, the protrusion portion can extend toward a collar covering the back of the user or even to the collar such that the temperature conducting member arranged on the protrusion portion can contact the human back, so as to allow the temperature conducting member to transmit cold or heat to the human back, making it possible to realize temperature regulation even for the back area covered by the collar, meeting the need for cooling or hot compress massage on the human back and improving the user experience of the user.

Abstract: The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection.

Abstract: The present disclosure provides a method for forming a semiconductor package and the semiconductor package. The method comprises attaching an interconnect device to a semiconductor substrate, and flip-chip mounting at least two chips over the interconnect device and the semiconductor substrate. Each chip includes first conductive bumps of a first height and second conductive bumps of a second height formed on a front side hereof, the second height being greater than the first height. The method further comprises bonding the second conductive bumps of each of the at least two chips to the upper surface of the semiconductor substrate while bonding the first conductive bumps of each of the at least two chips to the upper surface of the interconnect device Thus, the method uses a relatively simple and low-cost packaging process to achieve high-density interconnection wiring in a package.

Abstract: A DGT passive sampling device for water body detection includes a bottom fixed unit, where the bottom fixed unit includes an inserting drill bit; a passive sampling unit arranged at the top of the bottom fixed unit; and a floating marking unit arranged at the top of the passive sampling unit, where the floating marking unit includes a winding cylinder I, and the winding cylinder I is movably connected to the chassis by control inner ropes. After the inserting drill bit is inserted into the underwater soils, the bottom cavity winding source is started, the rotation of the bottom cavity roll releases the downward movement of the middle ropes, so that the passive sampling unit falls, while the bottom cavity roll may make the passive sampling unit regularly distributed at different heights of the water bottom by releasing different lengths of the middle ropes.

Abstract: The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device, a carrier board, and a clamping board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; and injecting a molding compound through one or more openings in one or both of the carrier board and the clamping board to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device.

Abstract: A portable blowing device configured for being worn around a neck of a human body is disclosed. The portable blowing device includes two parts and two first fans. Each part defines an airflow channel and includes an inner side wall, an outer side wall, and a top side wall. Each fan is received in one corresponding part and configured for generating an airflow to flow through the airflow channel defined therein. At least a portion of each of the two top side walls includes an inclined surface. Each part defines at least one first air inlet and at least one first air outlet communicated with the at least one first air inlet and the airflow channel, and each of the first air outlets is defined in one corresponding inclined surface.