Abstract: A method of forming a package is provided. The method comprises assembling on a carrier a stack of chip layers including a plurality of first chip layers and a second chip layer; encapsulating the stack of chip layers in a molding compound; removing the carrier to form a package main body; forming a redistribution layer on an exposed side of a first chip layer; and dividing the package main body to form a plurality of packages. Each first chip layer includes first chips and chip couplers. A chip package includes at least one chip stack and at least one chip coupler stack on a singulated redistribution layer. Each chip stack includes at least one chip from each chip layer, and each chip coupler stack includes at least one chip coupler and/or at least one chip coupler segment from each of the first chip layers.

Abstract: Disclosed herein are self-mixing interferometry (SMI) sensors, such as may include vertical cavity surface emitting laser (VCSEL) diodes and resonance cavity photodetectors (RCPDs). Structures for the VCSEL diodes and RCPDs are disclosed. In some embodiments, a VCSEL diode and an RCPD are laterally adjacent and formed from a common set of semiconductor layers epitaxially formed on a common substrate. In some embodiments, a first and a second VCSEL diode are laterally adjacent and formed from a common set of semiconductor layers epitaxially formed on a common substrate, and an RCPD is formed on the second VCSEL diode. In some embodiments, a VCSEL diode may include two quantum well layers, with a tunnel junction layer between them. In some embodiments, an RCPD may be vertically integrated with a VCSEL diode.

Abstract: Embodiments are directed to electronic devices that include a surface emitting laser array including a first set of light emitters distributed across the surface emitting laser array and configured to emit laser light into an environment of the electronic device. The laser array can also include a second set of light emitters interspersed with the first set of light emitters, where each light emitter in the second set of light emitters includes a first set of layers defining a first mirror, a second set of layers defining a second mirror, and a third set of layers positioned between the first set of layers and the second set of layers and defining a laser cavity. The surface emitting laser array can include a light blocking material positioned on one or more of the second set of light emitters and configured to cause localized heating of the laser array.

Abstract: A portable temperature regulation device defining a wear space, includes a main body, a protrusion portion, and a temperature conducting member at least partly arranged on the protrusion portion. The main body has a first side and a second side. The protrusion portion extends from the first side in a direction away from the second side. In use, the protrusion portion can extend toward a collar covering the back of the user or even to the collar such that the temperature conducting member arranged on the protrusion portion can contact the human back, so as to allow the temperature conducting member to transmit cold or heat to the human back, making it possible to realize temperature regulation even for the back area covered by the collar, meeting the need for cooling or hot compress massage on the human back and improving the user experience of the user.

Abstract: The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection.

Abstract: The present disclosure provides a method for forming a semiconductor package and the semiconductor package. The method comprises attaching an interconnect device to a semiconductor substrate, and flip-chip mounting at least two chips over the interconnect device and the semiconductor substrate. Each chip includes first conductive bumps of a first height and second conductive bumps of a second height formed on a front side hereof, the second height being greater than the first height. The method further comprises bonding the second conductive bumps of each of the at least two chips to the upper surface of the semiconductor substrate while bonding the first conductive bumps of each of the at least two chips to the upper surface of the interconnect device Thus, the method uses a relatively simple and low-cost packaging process to achieve high-density interconnection wiring in a package.

Abstract: A DGT passive sampling device for water body detection includes a bottom fixed unit, where the bottom fixed unit includes an inserting drill bit; a passive sampling unit arranged at the top of the bottom fixed unit; and a floating marking unit arranged at the top of the passive sampling unit, where the floating marking unit includes a winding cylinder I, and the winding cylinder I is movably connected to the chassis by control inner ropes. After the inserting drill bit is inserted into the underwater soils, the bottom cavity winding source is started, the rotation of the bottom cavity roll releases the downward movement of the middle ropes, so that the passive sampling unit falls, while the bottom cavity roll may make the passive sampling unit regularly distributed at different heights of the water bottom by releasing different lengths of the middle ropes.

Abstract: The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device, a carrier board, and a clamping board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; and injecting a molding compound through one or more openings in one or both of the carrier board and the clamping board to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device.

Abstract: A portable blowing device configured for being worn around a neck of a human body is disclosed. The portable blowing device includes two parts and two first fans. Each part defines an airflow channel and includes an inner side wall, an outer side wall, and a top side wall. Each fan is received in one corresponding part and configured for generating an airflow to flow through the airflow channel defined therein. At least a portion of each of the two top side walls includes an inclined surface. Each part defines at least one first air inlet and at least one first air outlet communicated with the at least one first air inlet and the airflow channel, and each of the first air outlets is defined in one corresponding inclined surface.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-stage assembly, including: align and fix at least one first-stage device to a target position on a carrier plate by utilizing the self-alignment capability of first-stage alignment solder joints; and while using a clamping board to support an exposed side of the at least one first-stage device, performing injection molding through an opening in the carrier board or the clamping board. The packaging method further comprises align and fix a second-stage device to a target position on the first-stage assembly by utilizing the self-alignment capability of second-level alignment solder joints between the first-stage assembly and the second-stage device.

Abstract: The present disclosure provides a method for forming a semiconductor package and the semiconductor package. The method comprises attaching an interconnect device to a semiconductor substrate, and flip-chip mounting at least two chips over the interconnect device and the semiconductor substrate. Each chip includes at least one first bump of a first height and at least one second bump of a second height formed on a front surface hereof, the second height being greater than the first height. The method further comprises bonding the at least one second conductive bump of each of the at least two chips to the upper surface of the semiconductor substrate and bonding the first conductive bump of each of the at least two chips to the upper surface of the interconnect device Thus, the method uses a relatively simple and low cost packaging process to achieve high-density interconnection wiring in a package.

Abstract: The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.

Abstract: A method of forming a package comprises forming a stack of chip layers. Each chip layer has a front side facing away from the carrier substrate. A first chip layer includes a plurality of first chips having first chip contacts on the front side of the first chip layer and chip couplers having through vias. A second chip layer includes a plurality of second chip having second chip contacts on the front side of the second chip layer and coupled to respective ones of at least a first subset of the through vias. The method further comprises forming a redistribution layer on the front side of the first chip layer and dividing the stack of chip layers and the redistribution layer to form a plurality of chip packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.

Abstract: A portable blowing device includes a body and fans arranged in the body. Air channels are arranged in the body and extend in the length direction of the body to allow airflow to pass through. Wind shields are arranged in the air channels, and a periphery of the wind shield is closely connected with a side wall of the air channel so that a sub-air channel is formed between the wind shield and the side wall of the air channel. Air outlets are formed in the side wall for communicating with outside and the sub-air channel, and airflow generated by the fan can enter the sub-air channel and then exits the air outlets. Because of the reduced volume of the sub-air channel, the airflow is concentrated after entering the sub-air channel, and airflow exiting the air outlets is strengthened, so that the cooling effect and the user experience are improved.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are described herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on an active surface of each semiconductor device in addition to connection terminals. A plurality of second alignment solder parts are formed on a surface of the carrier board.

Abstract: A new acoustic technique, tensile acoustic rheometry (TAR) for performing rheology measurement of a soft viscoelastic material sample is provided. In TAR, an excitation acoustic pulse is applied using a focused ultrasound transducer to a sample material to induce oscillatory motion of the sample. To track this induced motion, high repetition frequency ultrasound pulse-echo technique is used using a co-linear, con-focal ultrasound transducer that detects the backscattered echo signal from a surface or an interface of the sample. The detection ultrasound transducer system converts the echo signals to an electrical signal, and a processor determines a displacement of the interface of the sample as a function of time. The processor also determines the spectrogram, or the frequency spectrum of the dynamic surface movement of the sample material as a function of the time. Viscoelastic properties of the material are then determined from the displacement and the spectrogram measurements.