Abstract: The present invention provides an improved visual laryngeal mask comprising a tube, an end of the tube is provided with a fixing seat. The fixing seat is provided with an airbag, and the fixing seat has a recess which is provided with an airway opening. An imaging cavity extends longitudinally inside an inner wall of the tube. The imaging cavity has a built-in imaging device, and the imaging cavity protrudes forward relative to the airway opening to form a stopper which prevents an epiglottis from blocking the imaging device. A front end of the stopper is concaved to form a recess, and an opening of the imaging cavity is located at a low point of the recess.

Abstract: Disclosed herein are self-mixing interferometry (SMI) sensors, such as may include vertical cavity surface emitting laser (VCSEL) diodes and resonance cavity photodetectors (RCPDs). Structures for the VCSEL diodes and RCPDs are disclosed. In some embodiments, a VCSEL diode and an RCPD are laterally adjacent and formed from a common set of semiconductor layers epitaxially formed on a common substrate. In some embodiments, a first and a second VCSEL diode are laterally adjacent and formed from a common set of semiconductor layers epitaxially formed on a common substrate, and an RCPD is formed on the second VCSEL diode. In some embodiments, a VCSEL diode may include two quantum well layers, with a tunnel junction layer between them. In some embodiments, an RCPD may be vertically integrated with a VCSEL diode.

Abstract: The present invention provides an improved visual laryngeal mask comprising a snorkel, an end of the snorkel is provided with a fixing seat. The fixing seat is provided with an airbag, and the fixing seat has a recess which is provided with an airway opening. The inner wall of the snorkel longitudinally extends an imaging cavity and a cleaning channel. The imaging cavity has a built-in imaging device, and the imaging cavity and the cleaning channel protrude forward relative to the airway opening to form a stopper which prevents an epiglottis from blocking the imaging device.

Abstract: The application provides a semiconductor packaging structure, a semiconductor packaging method, a semiconductor packaging device and an electronic product. The semiconductor packaging structure comprises a substrate, at least one packaged component, a redistribution layer and a passivation layer. The substrate has at least one groove and the at least one packaged component is fixed in the at least one groove in one-to-one correspondence. Each packaged component is separated from a corresponding groove, in which the package component is disposed, by insulating materials. The at least one packaged component has first bonding pads on at least one active surface facing away from the substrate and are flush. The redistribution layer is formed using wafer fabrication process over the at least one active surface. The substrate includes a semiconductor material or insulating material with a thermal expansion coefficient that is the same as or similar to that of a base semiconductor material in the packaged component.

Abstract: A closed-loop stepper motor control system, drive device and automation device, wherein the system comprises a microprocessor (1) compatible with EtherCAT communication protocol functions, an external interface circuit (2) connected to the said microprocessor (1) and communication interface unit (3); the said microprocessor (1) is also connected to a drive circuit (4), current testing circuit (5), as well as an encoder feedback circuit (6); the said communication interface unit (3) is mutually connected to the said microprocessor (1) through the physical layer communication circuit (31); the said microprocessor (1) is also mutually connected to the power supply circuit (7) that provides stable power supply voltage.

Abstract: The application provides a semiconductor packaging structure, a semiconductor packaging method, a semiconductor packaging device and an electronic product. The semiconductor packaging structure comprises a substrate, at least one packaged component, a redistribution layer and a passivation layer. The substrate has at least one groove and the at least one packaged component is fixed in the at least one groove in one-to-one correspondence. Each packaged component is separated from a corresponding groove, in which the package component is disposed, by insulating materials. The at least one packaged component has first bonding pads on at least one active surface facing away from the substrate and are flush. The redistribution layer is formed over the at least one active surface. The substrate includes a semiconductor material or insulating material with a thermal expansion coefficient that is the same as or similar to that of a base semiconductor material in the packaged component.

Abstract: A portable blowing device includes a body and fans arranged in the body. Air channels are arranged in the body and extend in the length direction of the body to allow airflow to pass through. Wind shields are arranged in the air channels, and a periphery of the wind shield is closely connected with a side wall of the air channel so that a sub-air channel is formed between the wind shield and the side wall of the air channel. Air outlets are formed in the side wall for communicating with outside and the sub-air channel, and airflow generated by the fan can enter the sub-air channel and then exits the air outlets. Because of the reduced volume of the sub-air channel, the airflow is concentrated after entering the sub-air channel, and airflow exiting the air outlets is strengthened, so that the cooling effect and the user experience are improved.

Abstract: The application provides a semiconductor packaging structure, a semiconductor packaging method, a semiconductor packaging device and an electronic product. The semiconductor packaging structure comprises a substrate, at least one packaged component, a redistribution layer and a passivation layer. The substrate has at least one groove and the at least one packaged component is fixed in the at least one groove in one-to-one correspondence. Each packaged component is separated from a corresponding groove, in which the package component is disposed, by insulating materials. The at least one packaged component has first bonding pads on at least one active surface facing away from the substrate and are flush. The redistribution layer is formed over the at least one active surface. The substrate includes a semiconductor material or insulating material with a thermal expansion coefficient that is the same as or similar to that of a base semiconductor material in the packaged component.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-level assembly, including: align and fix at least one first-level device to a target position on a carrier plate by utilizing the self-alignment capability of first-level alignment solder joints; encapsulating the at least one first-level device to form a molded package body; and exposing the first-level interconnect terminals from the molded package body. The packaging method further comprises align and fix a second-level device to a target position on the first-level assembly by utilizing the self-alignment capability of second-stage alignment solder joints between the first-level assembly and the second-level device. The packaging method improves the operation speed and accuracy of the picking and placing of the first-level device and the second-level device, resulting in improved process efficiency and reduced process cost.

Abstract: An optoelectronic device includes a semiconductor substrate. A first set of thin-film layers is disposed on the substrate and defines a lower distributed Bragg-reflector (DBR) stack. A second set of thin-film layers is disposed over the lower DBR stack and defines an optical emission region, which is contained in a mesa defined by multiple trenches, which are disposed around the optical emission region without fully surrounding the optical emission region. A third set of thin-film layers is disposed over the optical emission region and defines an upper DBR stack. Electrodes are disposed around the mesa in gaps between the trenches and are configured to apply an excitation current to the optical emission region.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-stage assembly, including: align and fix at least one first-stage device to a target position on a carrier plate by utilizing the self-alignment capability of first-stage alignment solder joints; and while using a clamping board to support an exposed side of the at least one first-stage device, performing injection molding through an opening in the carrier board or the clamping board. The packaging method further comprises align and fix a second-stage device to a target position on the first-stage assembly by utilizing the self-alignment capability of second-level alignment solder joints between the first-stage assembly and the second-stage device.

Abstract: A portable blowing device configured for being worn around a neck of a human body, includes two arms each defining an airflow channel therein; and fans received in the arms respectively. The arm includes an inner side wall close to the neck and an outer side wall connected to the inner side wall. The arm includes an air inlet and an air outlet in communication with the airflow channel respectively. The air inlet is arranged at the inner side wall and/or the outer side wall. The fan is configured to generate an airflow passing through the air inlet, the airflow channel and the air outlet in sequence.

Abstract: A semiconductor assembly packaging method comprises aligning and attaching at least one first semiconductor device to a first side of an interconnect board by forming a plurality of first alignment solder joints; aligning and attaching at least one second semiconductor device to a second side of the interconnect board by forming a plurality of second alignment solder joints; pressing the at least one first semiconductor device toward the interconnect board while the first alignment solder joints are in a molten or partially molten state to form first interconnect bonds between the at least one first semiconductor device and the interconnect board; and pressing the at least one second semiconductor device toward the interconnect board while the second alignment solder joints are in a molten or partially molten state to form second interconnect bonds between the at least one second semiconductor device and the interconnect board. A semiconductor component is made using the method.

Abstract: A robot and a system for a medical operation of corona viruses e.g., COVID-19 sampling are provided. The robot includes a resilient connector, connecting plates connected with the resilient connector, stretchable and retractable assemblies, a driving assembly and a flexible sampling assembly; two ends of the stretchable and retractable assembly are respectively connected with adjacent two connecting plates, the stretchable and retractable assembly includes stretchable and retractable components divided into at least two stretchable and retractable groups and arranged around the resilient connector, the driving assembly drive the stretchable and retractable component to be switchably stretched or retracted, the flexible sampling assembly is configured to collect COVID-19 specimens of respiratory tract. The robot can be bent and moved freely in special-shaped human respiratory tract, realize secretions sampling of human respiratory tract and reduce pain and difficulty of examination.

Abstract: A semiconductor assembly packaging method, a semiconductor assembly and an electronic device are provided. The method comprises providing an interconnect board and at least one semiconductor device; aligning and attaching the at least one semiconductor device to the interconnect board by forming a plurality of alignment solder joints; applying pressure to the at least one semiconductor device and/or the interconnect board while the alignment solder joints are in a molten or partially molten state, whereby first connection terminals on the interconnect board are joined with and bonded to corresponding second connection terminals on the at least one semiconductor device. Using the packaging method, the semiconductor device and the interconnect board can be aligned accurately using relatively simple and low cost processes and equipment. The method can also be used to align and bond at least one semiconductor device to another semiconductor device.

Abstract: A method of forming a package comprises assembling at least one chip layer over a carrier substrate, the at least one chip layer including chip couplers and chips, each of the chips having a front side facing the carrier substrate and chip contacts formed on the front side, the couplers including first chip couplers, each of the first chip couplers having an upper side facing away from the carrier substrate and first bumps formed on the upper side. The method further comprises encapsulating the at least one chip layer to form a molded package structure, thinning the molded package structure to expose the first bumps, forming a metal layer on a side of the molded package structure where the first bumps are exposed, removing the carrier to expose another side of the molded package structure, and forming a redistribution layer and second bumps on the molded package structure.

Abstract: The present disclosure provides a method for forming a semiconductor package and the semiconductor package. The method comprises attaching an interconnect device to a semiconductor substrate, and flip-chip mounting at least two chips over the interconnect device and the semiconductor substrate. Each chip includes at least one first bump of a first height and at least one second bump of a second height formed on a front surface hereof, the second height being greater than the first height. The method further comprises bonding the at least one second conductive bump of each of the at least two chips to the upper surface of the semiconductor substrate and bonding the first conductive bump of each of the at least two chips to the upper surface of the interconnect device Thus, the method uses a relatively simple and low cost packaging process to achieve high-density interconnection wiring in a package.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device, a carrier board, and a clamping board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; and injecting a molding compound through one or more openings in one or both of the carrier board and the clamping board to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device.

Abstract: The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.