Abstract: A uniformly radiation intensity generation box by symmetrical lighting source is constructed to include a housing, the housing having a top opening for the mounting of a camera for taking photos of a real object and a door at one side, a plurality of lamp tubes vertically symmetrically provided inside the housing, and a plurality of diffusion plates mounted inside the housing and covered over the lamp tubes, each diffusion plate having a plurality of diffusing grains uniformly arranged in one face thereof and adapted for diffusing light from the lamp tubes in all directions inside the housing.

Abstract: A method and apparatus to obtain a substantially accurate digital color image of a subject at relatively low cost. A moveable enclosure containing a controlled lighting source provides a controlled lighting environment that costs considerably less than a traditional photo studio and is more convenient to use for many applications. A digital color image capture device captures an image of a subject in the enclosure. The captured image is sent to a computer where a stored color profile previously obtained from a calibration of the digital image capture device is used by a software program to automatically correct the color of the captured image. The color-corrected image can then be distributed to other computers for display.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: The present invention provides a transmission method capable of synchronously transferring information in many ways to simultaneously transfer data to plural receivers. In the transmission method of the present invention, a control menu and data to be transferred are first provided, and predetermined receivers are then selected. Next, an image capturing device is used to scan the control menu and the data to be transferred and convert them into an electric signal, which is then transferred to a computer server. The computer server discriminates the electric signal and converts it into an image signal. If the result of discrimination is successful, the image signal is transferred to an FTP server or a client computer so that the receivers can receive the image signal in predetermined ways of reception. The present invention has the characteristics of synchronous and manifold transmission, fast transmission, and convenient use.

Abstract: A method and system may process messages in real time. The computer may analyze the received message in advance when receiving a message from the sender, which means the computer may determine whether or not the received message is the specific message which needs to be processed in real time. If the received message is specific, then, according to the setting reminding method, the system may utilize shaking of the mouse, sending out voice or light or displaying an image on the screen to remind the users. The users thus may respond to the message immediately, which may eliminate the delay of the important message.

Abstract: A method and system for managing a digital image using online driving from a network are disclosed. A digital image is formed by a capturing device and then is stored in a first memory of the capturing device. Afterwards, a program media automatically diagnoses the capturing device and then installs a driver corresponding to the capturing device for online driving of the capturing device. The digital image in the first memory is uploaded to a second memory of the image server, and therefore the capacity of the first memory is completely released. Thereafter, the digital image is properly edited and is stored in the second memory to manage and distribute with respect to the digital image. Finally, a remote PC is linked to the image server via the Internet for selectively downloading the digital image saved in the secondary memory.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over tops and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, f) forming an intermediate layer on the second conducting layer, and g) removing the intermediate layer and partially removing the second conducting layer while retaining a portion of the second conducting layer with a rough top surface alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificia

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over top surfaces and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, and f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer and construct a capacitor plate with a generally crosssectionally modified T-

Abstract: A method and system for automatically parsing codes of Web pages and extracting contents of the Web pages. A computer program is utilized to decompose Web pages into a plurality of content blocks for users to flexibly select some desired content blocks according to their preferences and needs. Save a selection setting of the selected content blocks of Web pages and transmit the setting and the selected contents of Web pages to portable data processing gismos. Users thus could use portable data processing gismos to browse the information over the Internet and even use the selection setting to update the instant information of Web pages.

Abstract: A method of forming a DRAM cell with a trench capacitor over a semiconductor substrate comprises the following steps. First, an etching step is performed to form a trench structure in the substrate, wherein the trench structure has a bottom and sidewalls, and the sidewalls are adjacent to the bottom. And each the sidewall includes an upper sidewall adjacent to the substrate through a insulating layer and a lower sidewall adjacent to the substrate through a dielectric layer. Then, after the etching steps, a doped area is formed on the bottom and the lower sidewall for serving as the first electrode of the trench capacitor. A first conducting layer is formed on the doped area and the insulating layer above a portion of the upper sidewall to serve as a first capacitor electrode.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over top surfaces and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, and f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer and construct a capacitor plate with a generally crosssectionally modified T-

Abstract: The present invention provides a method of forming trench capacitor with a sacrificial silicon nitride. A deep trench structure is formed in a substrate. A TEOS oxide layer is formed on the substrate and filled in said trench region, etched to a first level subsequently, wherein a portion of the TEOS oxide layer is remained in the trench region and a portion of the substrate exposed to form a trench sidewall. A thermally oxidation process is performed to form a collar oxide on the exposed substrate. A silicon nitride sidewall is formed on the collar oxide, then removing the residual TEOS oxide layer by wet etching. The trench region is then etched using the silicon nitride sidewall as a barrier to form a bottle shape trench region for increasing the surface of the trench region. A bottom cell plate is formed in the fresh trench region. The silicon nitride sidewall is removed.

Abstract: The present invention provides a method for fabricating a field oxide on a semiconductor substrate. A first pad layer and a first mask layer is formed successively on the semiconductor substrate. An opening is formed in the first mask layer to define a region for forming the field oxide. A first field oxide is formed in the opening, which is then removed to form a concave portion. The first pad layer exposed by the concave portion is removed to form a cavity. A second pad layer having a smaller thickness than the first pad layer is formed on the semiconductor substrate. A mask portion is formed in the sidewall of the patterned first mask layer and the cavity. The mask portion in the sidewall of the patterned first mask layer has a thickness less than 300 Å. Finally, thermal oxidation is carried out to form a second field oxide in the concave portion.

Abstract: A method of removing a polysilicon buffer in a method of forming a field oxide and an active area is disclosed herein that comprises the step of applying an etching selectivity solution to the polysilicon buffer to substantially remove the polysilicon buffer without substantially affecting the field oxide, a pad oxide, and the substrate. An etching selectivity solution is defined herein is a solution that has an etching rate for one material that is higher than for another material. In this case, the etching selectivity solution has an etching rate for polysilicon material that is higher than its etching rate for field oxide material. Accordingly, when the etching selectivity solution is applied to the polysilicon buffer, it will substantially etch off the polysilicon buffer without substantially affecting the field oxide. In the preferred embodiment, the etching selectivity solution comprises a mixture of HF and HNO3, or HF, HNO3 and CH3COOH.

Abstract: A method of forming a field oxide isolation region includes: forming a first pad oxide layer over a semiconductor substrate; forming a silicon nitride layer over the first pad oxide layer; patterning and etching the silicon nitride layer and the first pad oxide layer to expose a portion of the substrate, and simultaneously forming an undercut cavity; forming a second pad oxide layer over the exposed portion of the substrate; depositing a layer of polysilicon over the second pad oxide layer, the polysilicon layer filling the undercut cavity to form a polysilicon plug; removing portions of the polysilicon layer to form a polysilicon spacer; thermally oxidizing the substrate to substantially consume the polysilicon spacer but leave a polysilicon residual of the polysilicon plug, the thermal oxidation forming a thick oxide above the exposed portion of the substrate; substantially removing the silicon nitride layer; applying a first etching solution to the first pad oxide layer and the polysilicon residual, the fi

Abstract: A method of forming a DRAM cell with a trench capacitor over a semiconductor substrate comprises the following steps. First, an etching step is performed to form a trench structure in the substrate, wherein the trench structure has a bottom and sidewalls, and the sidewalls are adjacent to the bottom. Then, the trench structure is doped to form a doping region on the bottom and a portion of the sidewalls. A selective etching step is performed to remove a portion of the doping region, wherein a selectivity of the doping region is higher than that of undoped sidewalls. A dielectric layer is formed on a top surface of the trench structure. A conducting layer is then formed in the trench structure. Next, a gate structure is formed on the substrate. A doping step is used to form the drain/source structures adjacent to the gate. A strap region is formed to couple the conducting layer and the drain/source structures.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over top surfaces and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, and f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer and construct a capacitor plate with a generally cross-sectionally modified T

Abstract: A method is provided for manufacturing a capacitor having a generally crosssectionally modified T-shaped structure with a rough surface to serve as a lower capacitor plate, and having another dielectric layer and another conducting layer to construct an upper capacitor plate. Such a structure not only significantly increases the surface area of the capacitor but is conducive to the subsequent planarization process.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer on tops and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer, and g) forming a rugged conducting layer on surfaces of the portion of the first conductin