Abstract: The present invention provides a method of forming trench capacitor with a sacrificial silicon nitride. A deep trench structure is formed in a substrate. A TEOS oxide layer is formed on the substrate and filled in said trench region, etched to a first level subsequently, wherein a portion of the TEOS oxide layer is remained in the trench region and a portion of the substrate exposed to form a trench sidewall. A thermally oxidation process is performed to form a collar oxide on the exposed substrate. A silicon nitride sidewall is formed on the collar oxide, then removing the residual TEOS oxide layer by wet etching. The trench region is then etched using the silicon nitride sidewall as a barrier to form a bottle shape trench region for increasing the surface of the trench region. A bottom cell plate is formed in the fresh trench region. The silicon nitride sidewall is removed.

Abstract: The present invention provides a method for fabricating a field oxide on a semiconductor substrate. A first pad layer and a first mask layer is formed successively on the semiconductor substrate. An opening is formed in the first mask layer to define a region for forming the field oxide. A first field oxide is formed in the opening, which is then removed to form a concave portion. The first pad layer exposed by the concave portion is removed to form a cavity. A second pad layer having a smaller thickness than the first pad layer is formed on the semiconductor substrate. A mask portion is formed in the sidewall of the patterned first mask layer and the cavity. The mask portion in the sidewall of the patterned first mask layer has a thickness less than 300 Å. Finally, thermal oxidation is carried out to form a second field oxide in the concave portion.

Abstract: A method of removing a polysilicon buffer in a method of forming a field oxide and an active area is disclosed herein that comprises the step of applying an etching selectivity solution to the polysilicon buffer to substantially remove the polysilicon buffer without substantially affecting the field oxide, a pad oxide, and the substrate. An etching selectivity solution is defined herein is a solution that has an etching rate for one material that is higher than for another material. In this case, the etching selectivity solution has an etching rate for polysilicon material that is higher than its etching rate for field oxide material. Accordingly, when the etching selectivity solution is applied to the polysilicon buffer, it will substantially etch off the polysilicon buffer without substantially affecting the field oxide. In the preferred embodiment, the etching selectivity solution comprises a mixture of HF and HNO3, or HF, HNO3 and CH3COOH.

Abstract: A method of forming a field oxide isolation region includes: forming a first pad oxide layer over a semiconductor substrate; forming a silicon nitride layer over the first pad oxide layer; patterning and etching the silicon nitride layer and the first pad oxide layer to expose a portion of the substrate, and simultaneously forming an undercut cavity; forming a second pad oxide layer over the exposed portion of the substrate; depositing a layer of polysilicon over the second pad oxide layer, the polysilicon layer filling the undercut cavity to form a polysilicon plug; removing portions of the polysilicon layer to form a polysilicon spacer; thermally oxidizing the substrate to substantially consume the polysilicon spacer but leave a polysilicon residual of the polysilicon plug, the thermal oxidation forming a thick oxide above the exposed portion of the substrate; substantially removing the silicon nitride layer; applying a first etching solution to the first pad oxide layer and the polysilicon residual, the fi

Abstract: A method of forming a DRAM cell with a trench capacitor over a semiconductor substrate comprises the following steps. First, an etching step is performed to form a trench structure in the substrate, wherein the trench structure has a bottom and sidewalls, and the sidewalls are adjacent to the bottom. Then, the trench structure is doped to form a doping region on the bottom and a portion of the sidewalls. A selective etching step is performed to remove a portion of the doping region, wherein a selectivity of the doping region is higher than that of undoped sidewalls. A dielectric layer is formed on a top surface of the trench structure. A conducting layer is then formed in the trench structure. Next, a gate structure is formed on the substrate. A doping step is used to form the drain/source structures adjacent to the gate. A strap region is formed to couple the conducting layer and the drain/source structures.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over top surfaces and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, and f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer and construct a capacitor plate with a generally cross-sectionally modified T

Abstract: A method is provided for manufacturing a capacitor having a generally crosssectionally modified T-shaped structure with a rough surface to serve as a lower capacitor plate, and having another dielectric layer and another conducting layer to construct an upper capacitor plate. Such a structure not only significantly increases the surface area of the capacitor but is conducive to the subsequent planarization process.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer on tops and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer, and g) forming a rugged conducting layer on surfaces of the portion of the first conductin

Abstract: A method is provided for manufacturing a capacitor with a unique sturcture. The capacitor includes a structure formed in the dielectric layer and the etching stop layer and forming a contact window, a conducting material-adhering layer formed on a portion of the etching stop layer neighboring to the contact window, a first conducting layer filling in the contact window and upwardly extended to form a generally cross-sectionally modified T-shaped structure with a rough top surface, and a rugged conducting layer formed inside the first conducting layer and on the conducting material-adhering layer. This method significantly increases the density and intensity of the capacitor.

Abstract: A method for manufacturing a capacitor, applied to a memory unit having a substrate forming thereon a dielectric layer, includes the steps of a) forming a sacrificial layer over the dielectric layer, b) partially removing the sacrificial layer and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, f) removing the portion of the sacrificial layer to expose the dielectric layer, g) forming a third conducting layer over surfaces of the portion of the first conducting layer, the second conducting layer, and the dielectric layer, and h) partially removing the third conducting layer while retaining a portion of the third conducting l

Abstract: A driver circuit is to be used with an attachment unit interface in a network system and receives complementary data signals and an enable signal from constant current source and a differential transistor pair which includes a pair of differential transistors and a pair of load resistors. Each of the differential transistors has a gate terminal which receives one of the complementary data signals, a drain terminal which is connected to one of the load resistors, and a source terminal which is connected to the constant current source. A switch network is connected to the drain terminal of the differential transistors and is activated by the enable signal so as to generate a differential voltage output. Each of a pair of source followers has a gate terminal connected to the switch network and a source terminal The source followers receive the differential voltage output from the switch network.