Patents by Inventor Wei SHENG

Wei SHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11665058
    Abstract: During operation, an electronic device receives a packet or a frame associated with a second electronic device, where the packet or the frame includes information specifying a factory reset command. For example, the second electronic device may be a dynamic host configuration protocol (DHCP) server or may perform functions of a DHCP server. Moreover, the packet or the frame may include an acknowledgment (ACK) in a discover, offer, request and acknowledgment (DORA) procedure, and the information may be included in an option 43 subfield or an option 52 subfield in the packet or the frame. In response to receiving the factory reset command, the electronic device performs a factory reset. Note that the factory reset may restore firmware in the electronic device to a factory-fresh version and a configuration of the electronic device to a factory-fresh state, may erase memory in the electronic device.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: May 30, 2023
    Assignee: ARRIS Enterprises, LLC
    Inventors: Subash Tirupachur Comerica, Wenge Ren, Wei Sheng Hsu, Craig Owens
  • Publication number: 20230148005
    Abstract: Described herein are macrocyclic compounds of Formula (I), which can inhibit kinases such as EGFR, including mutant forms such as T790M EGFR mutants. Also described herein are pharmaceutical compositions comprising a compound of Formula (I), or any pharmaceutically acceptable form thereof, processes for their preparation, and use in therapy for the prevention or treatment of cancer. In particular, compounds described herein can be effective for treating EGFR-driven cancers including non-small cell lung cancer (NSCLC).
    Type: Application
    Filed: February 18, 2021
    Publication date: May 11, 2023
    Inventors: Wei-Sheng Huang, William C. SHAKESPEARE, Charles J. EYERMANN, David C. DALGARNO
  • Publication number: 20230140517
    Abstract: A computer network device that performs key matching is described. While attempting to establish a secure connection with an electronic device, the computer network device may receive a connection-request message associated with the electronic device. In response, the computer network device may provide a context message addressed to a computer, where the context message requests stored passphrase information associated with the electronic device. Then, the computer network device may receive, associated with the computer, a context response. When the context response indicates that there is no stored passphrase information associated with the electronic device, the computer network device may perform the key matching to identify the passphrase associated with the electronic device. Next, the computer network device may provide, addressed to the computer, the identified passphrase associated with the electronic device or an encryption key corresponding to the identified passphrase for storage by the computer.
    Type: Application
    Filed: October 19, 2022
    Publication date: May 4, 2023
    Applicant: ARRIS Enterprises LLC
    Inventors: Wei-Sheng Hsu, Chiu-Yi Li, Weichih Huang
  • Publication number: 20230121202
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor fin. The semiconductor structure also includes a first nanowire vertically overlapping a top surface of the semiconductor fin, a second nanowire vertically overlapping the first nanowire, and a third nanowire vertically overlapping the second nanowire. The semiconductor structure further includes a gate wrapping around the first nanowire, the second nanowire, and the third nanowire. A first portion of the gate vertically sandwiched between the first nanowire and the second nanowire is greater than a second portion of the gate vertically sandwiched between the second nanowire and the third nanowire.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsuan HSIAO, Wei-Sheng YUN, Winnie Victoria Wei-Ning CHEN, Tung Ying LEE, Ling-Yen YEH
  • Publication number: 20230123795
    Abstract: A method and apparatus for dicing optical devices from a substrate are described herein. The method includes the formation of a plurality of trenches using radiation pulses delivered to the substrate. The radiation pulses are delivered in a pattern to form trenches with varying depth as the trenches extend outward from a top surface of the optical device. The varying depth of the trenches provides edges of each of the optical devices which are slanted. The radiation pulses are UV radiation pulses and are delivered in bursts around the silhouette of the optical devices.
    Type: Application
    Filed: September 15, 2022
    Publication date: April 20, 2023
    Inventors: Wei-Sheng LEI, Zhengping YAO, Mahendran CHIDAMBARAM, Kangkang WANG, Zhihong John LIN, Ludovic GODET, Visweswaren SIVARAMAKRISHNAN
  • Publication number: 20230113276
    Abstract: Methods and apparatuses for processing lithium batteries with a laser source having a wide process window, high efficiency, and low cost are provided. The laser source is adapted to achieve high average power and a high frequency of picosecond pulses. The laser source can produce a line-shaped beam either in a fixed position or in scanning mode. The system can be operated in a dry room or vacuum environment. The system can include a debris removal mechanism, for example, inert gas flow, to the processing site to remove debris produced during the patterning process.
    Type: Application
    Filed: September 16, 2022
    Publication date: April 13, 2023
    Inventors: Wei-Sheng LEI, Girish Kumar GOPALAKRISHNAN NAIR, Kent Qiujing ZHAO, Daniel STOCK, Tobias STOLLEY, Thomas DEPPISCH, Jean DELMAS, Kenneth S. LEDFORD, Subramanya P. HERLE, Kiran VACHHANI, Mahendran CHIDAMBARAM, Roland TRASSL, Neil MORRISON, Frank SCHNAPPENBERGER, Kevin Laughton CUNNINGHAM, Stefan BANGERT, James CUSHING, Visweswaren SIVARAMAKRISHNAN
  • Publication number: 20230109033
    Abstract: An ionic liquid catalyst and a method for manufacturing the same are provided. The ionic liquid catalyst includes a carrier. The carrier contains nickel ferrite as a component, and an outer surface of the carrier is modified to have a decolorant and a degradation agent. The decolorant is grafted onto nickel atoms of the carrier, and the degradation agent is grafted onto iron atoms of the carrier. The method includes: providing the carrier that contains nickel ferrite as a component; and modifying the carrier, so that the nickel atoms of the carrier are grafted with the decolorant and the iron atoms of the carrier are grafted with the degradation agent. Accordingly, the ionic liquid catalyst is obtained.
    Type: Application
    Filed: July 10, 2022
    Publication date: April 6, 2023
    Inventors: TE-CHAO LIAO, SEN-HUANG HSU, WEI-SHENG CHENG
  • Publication number: 20230106419
    Abstract: A polyvinyl chloride artificial leather without a foaming structure is provided. The polyvinyl chloride artificial leather includes a base fabric layer and a top fabric layer directly formed on the base fabric layer. The top fabric layer has a solid structure extendedly formed from one surface of the top fabric layer to the base fabric layer, and the solid structure is formed by a fabric composition. The solid structure has a predetermined thickness. The fabric composition includes 40 to 70 parts by weight of a polyvinyl chloride resin and 30 to 60 parts by weight of a polymer plasticizer. A weight average molecular weight of the polymer plasticizer is within a range from 1,500 to 6,000, a molecular structure of the polymer plasticizer has at least one soft segment that is in a linear shape, and the at least one soft segment has an ether group.
    Type: Application
    Filed: September 5, 2022
    Publication date: April 6, 2023
    Inventors: TE-CHAO LIAO, WEI-SHENG CHENG, CHAO-TUNG WU
  • Patent number: 11621194
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 4, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
  • Patent number: 11621344
    Abstract: A device includes a semiconductor fin, a first epitaxy structure and a gate stack. The semiconductor fin protrudes from a substrate. The first epitaxy feature laterally surrounds a first portion of the semiconductor fin. The gate stack laterally surrounds a second portion of the semiconductor fin above the first portion of the semiconductor fin, wherein the second portion of the semiconductor fin has a lower surface roughness than the first epitaxy feature.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Tung-Ying Lee, Chih-Chieh Yeh
  • Publication number: 20230102829
    Abstract: Compounds and pharmaceutical compositions that modulate kinase activity, including mutant EGFR and mutant HER2 kinase activity, and compounds, pharmaceutical compositions, and methods of treatment of diseases and conditions associated with kinase activity, including mutant EGFR and mutant HER2 activity, are described herein.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 30, 2023
    Inventors: WEI-SHENG HUANG, YONGJIN GONG, FENG LI, NICHOLAS E. BENCIVENGA, DAVID C. DALGARNO, ANNA KOHLMANN, WILLIAM C. SHAKESPEARE, RANNY M. THOMAS, XIAOTIAN ZHU, ANGELA V. WEST, WILLMEN YOUNGSAYE, YUN ZHANG, TIANJUN ZHOU
  • Patent number: 11616146
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chao Lin, Wei-Sheng Yun, Tung-Ying Lee
  • Patent number: 11605562
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Tzu-Chung Wang, Kai-Tai Chang, Wei-Sheng Yun
  • Publication number: 20230062055
    Abstract: A method for recycling polyester fabrics with use of an ionic liquid catalyst is provided, which includes: providing a recycled polyester fabric; and using a chemical de-polymerization liquid to chemically de-polymerize the recycled polyester fabric and form a de-polymerization product that includes bis-2-hydroxylethyl terephthalate (BHET). The chemical de-polymerization liquid is used to chemically de-polymerize the recycled polyester fabric in an environment where a de-polymerization catalyst exists, and the de-polymerization catalyst is the ionic liquid catalyst in a solid state.
    Type: Application
    Filed: June 26, 2022
    Publication date: March 2, 2023
    Inventors: TE-CHAO LIAO, JUNG-JEN CHUANG, WEI-SHENG CHENG, ZHANG-JIAN HUANG, Yu-Ti Tseng
  • Publication number: 20230060362
    Abstract: A method for improving hue of recycled bis-2-hydroxylethyl terephthalate by using ionic liquids including providing a recycled polyester fabric; using a chemical de-polymerization liquid to chemically de-polymerize the recycled polyester fabric to form a de-polymerization product; mixing the de-polymerization product with water to form an aqueous phase liquid; dispersing an ionic liquid impurity adsorption material into the aqueous phase liquid to adsorb impurities originally present in the recycled polyester fabric.
    Type: Application
    Filed: June 24, 2022
    Publication date: March 2, 2023
    Inventors: TE-CHAO LIAO, JUNG-JEN CHUANG, WEI-SHENG CHENG, ZHANG-JIAN HUANG, Yu-Ti Tseng
  • Publication number: 20230061475
    Abstract: A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Sheng Yun
  • Patent number: 11594615
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 11581421
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Publication number: 20230000218
    Abstract: A clip-on strap assembly includes a watch strap with a groove and two mounting holes, a base disposed in the groove and including a midpoint connecting portion, two movable members movably on the base and located on opposite sides of the connecting portion, two snap hooks disposed on ends of the movable members, two elastic members disposed between the movable members and the connecting portion, and two pressing members disposed on the movable members and accommodated in the two mounting holes. The pressing members can bear against the elastic members. The snap hooks can engage with or be disengaged from the two buckles. The watch strap is clipped to or unclipped from the watch head merely by only pressing the two pressing members, facilitating the replacement of the watch strap.
    Type: Application
    Filed: June 16, 2022
    Publication date: January 5, 2023
    Inventors: YING-WEI SHENG, CHIEH KUO, DAI-HONG CAI
  • Publication number: 20230002268
    Abstract: A method and apparatus for substrate dicing are described. The method includes utilizing a laser to dice a substrate along a dicing path to form a perforated line around each device within the substrate. The dicing path is created by exposing the substrate to bursts of laser pulses at different locations around each device. The laser pulses are delivered to the substrate and may have a pulse repetition frequency of greater than about 25 MHz, a pulse width of less than about 15 picoseconds, and a laser wavelength of about 1.0 ?m to about 5 ?m.
    Type: Application
    Filed: June 9, 2022
    Publication date: January 5, 2023
    Inventors: Wei-Sheng LEI, Mahendran CHIDAMBARAM, Kangkang WANG, Ludovic GODET, Visweswaren SIVARAMAKRISHNAN