Patents by Inventor Wei SHENG

Wei SHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230350098
    Abstract: An optical stack structure includes a metal nanowire layer and an organic polymer layer. A crosslinking degree of the organic polymer layer is greater than or equal to 80% and less than or equal to 100%, and a content of volatile organic compounds in the organic polymer layer is less than or equal to 1%. The content of the volatile organic compounds in the organic polymer layer is defined as a difference between a thermal weight loss of the organic polymer layer measured at a measuring temperature and a water content of the organic polymer layer measured at the measuring temperature.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Inventors: Huang CHEN, Chng Mao HUANG, Wei Sheng CHEN
  • Publication number: 20230325330
    Abstract: A data transmission control device is provided. The data transmission control device is disposed in a chip that includes a Peripheral Component Interconnect Express (PCIe) interface, and the data transmission control device is coupled to a memory that includes a block. The data transmission control device includes: a control circuit, a PCIe interface controller, and an address monitoring circuit. The PCIe interface controller is configured to receive a data. The address monitoring circuit is configured to issue an interrupt to the control circuit when the data is written to the block.
    Type: Application
    Filed: March 17, 2023
    Publication date: October 12, 2023
    Inventors: Yan-Qing WANG, Yan-Xiong WU, Wei-Sheng DU, Qin-Wei SHE
  • Publication number: 20230309949
    Abstract: A wearable heart sound detection system, which includes an acoustic sensing device for collecting heart sound signals of the body, performing signal amplification, filtering, digitization and other preprocessing on the collected heart sound signals, and outputting the preprocessed heart sound signals; a computing electronic device communicatively coupled to the acoustic sensing device for acquiring the preprocessed heart sound signal, and a cloud data database communicatively coupled to the external computing electronic device. The acoustic device includes a capacitive sound sensor, a piezoelectric sound sensor and a circuit assembly. The circuit assembly is respectively electrically connected with the capacitive sound sensor and the piezoelectric sound sensor. The circuit assembly, the capacitive sound sensor and the piezoelectric sound sensor are integrated on a flexible substrate.
    Type: Application
    Filed: October 15, 2022
    Publication date: October 5, 2023
    Inventors: Yao-Sheng Chou, Wei-Sheng Su, Hsiao-Yi Lin
  • Patent number: 11776852
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Ming Yu, Tung Ying Lee, Wei-Sheng Yun, Fu-Hsiang Yang
  • Patent number: 11772984
    Abstract: An infrared reflective material, a method for producing the same, and an infrared reflective structure are provided. The method includes a preparation step implemented by mixing antimony and zirconium tungstate through a sol-gel manner to form zirconium tungstate composite powders doped with the antimony; a sintering step implemented by sintering the antimony and the zirconium tungstate in the zirconium tungstate composite powders doped with the antimony in a temperature gradient within a range from 500° C. to 1,100° C. for a predetermined time period, so that the antimony and the zirconium tungstate in the zirconium tungstate composite powders doped with the antimony bond together to form into composite tungsten oxide powders; a grinding step implemented by grinding the composite tungsten oxide powders; and a mixing step implemented by mixing the composite tungsten oxide powders that are grinded into an acrylic resin to form the infrared reflective material.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 3, 2023
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Sen-Huang Hsu, Wei-Sheng Cheng
  • Publication number: 20230307275
    Abstract: A purge port assembly for a wafer container includes a purge module configured to allow inlet flow of purge gas and a transition portion disposed over an intermediate outlet of the purge module. The transition portion includes a receiver configured to receive the purge gas discharged from the purge module, an outlet connector configured to attach with a diffuser, and an intermediate conduit. The intermediate conduit connects the receiver to the outlet connector and extends from the receiver at an acute angle relative to an axis of the inlet opening of the receiver. The intermediate conduit has a length that spaces apart the outlet connector from the receiver. A wafer container includes a shell and a purge port assembly. The shell includes an interior space. The purge port assembly extends through an opening in the shell into the interior space.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 28, 2023
    Inventors: Matthew A. Fuller, Wei Sheng Hsu, Kobold Yang, Colton J. Harr
  • Publication number: 20230304125
    Abstract: A method for recovering a valuable material from a perovskite solar cell includes immersing a perovskite solar cell device in an organic solvent to dissolve a monovalent metal cation, a divalent metal cation, and two halogen anions in the organic solvent, followed by adding an oxidizing agent and conducting a heating treatment to form a solid phase residue and a halogen molecule, dissolving the halogen molecule in deionized water to form a halogen solution, rinsing the solid phase residue with deionized water to obtain a solid phase and a liquid phase, calcining the solid phase into a metal oxide, or mixing the solid phase with the halogen solution to obtain a first metal halide, subjecting the liquid phase to an extraction treatment to form an oil phase layer, followed by conducting a back-extraction treatment, adding the halogen solution, and conducting a vacuum concentration treatment to obtain a second metal halide.
    Type: Application
    Filed: August 8, 2022
    Publication date: September 28, 2023
    Inventors: Fan-Wei LIU, Yu-Lun CHUEH, Wei-Sheng CHEN
  • Patent number: 11753404
    Abstract: The invention relates to c-Kit inhibitors useful in the treatment of cancers, and other serine-threonine kinase mediated diseases, having the Formula: wherein A, L, R1, R2, R3, and n are described herein.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: September 12, 2023
    Assignee: Ariad Pharmaceuticals, Inc.
    Inventors: Nicholas E. Bencivenga, David C. Dalgarno, Joseph M. Gozgit, Wei-Sheng Huang, Anna Kohlmann, Feng Li, Jiwei Qi, William C. Shakespeare, Ranny M. Thomas, Yihan Wang, Xiaotian Zhu
  • Publication number: 20230282498
    Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.
    Type: Application
    Filed: May 9, 2023
    Publication date: September 7, 2023
    Inventors: Kurtis LESCHKIES, Jeffrey L. FRANKLIN, Wei-Sheng LEI, Steven VERHAVERBEKE, Jean DELMAS, Han-Wen CHEN, Giback PARK
  • Patent number: 11744473
    Abstract: A convenient self-locking blood pressure cuff facilitating one-handed use by a user taking his own blood pressure includes a cuff belt, a casing assembly, and a self-locking structure. The self-locking structure is received in the casing assembly. The self-locking structure includes a core shaft, a locking assembly, and a pressing assembly. The core shaft is slidably connected to the casing assembly. The locking assembly and the pressing assembly are wrapped around the core shaft. The locking assembly can rotate when a free end of the cuff belt moves with respect to the casing assembly. The locking assembly can further press against the cuff belt when the core shaft slides in the casing assembly. The pressing assembly presses against the locking assembly to prevent the locking assembly from rotating back.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Jiangyu Kangjian Innovation Medical Technology(Chengdu) Co., Ltd
    Inventors: Ying-Wei Sheng, Chieh Kuo, Dai-Hong Cai, Ying-Chia Tang, Yu-Chao Li, Lien-Yu Lin, Xue-Pei Xu
  • Publication number: 20230273355
    Abstract: Methods of dicing optical devices from an optical device substrate are disclosed. The methods include disposing a protective coating only over the optical devices. The optical device substrate includes the optical devices disposed on the surface of the optical device substrate with areas therebetween. The areas of the optical device substrate are exposed by the protective coating. The protective coating includes a polymer, a solvent, and an additive. The methods further include curing the protective coating via a cure process so that the protective coating is water-soluble after the solvent is removed by the cure process, dicing the optical devices from the optical device substrate by projecting a laser beam to the areas between the optical devices, and exposing the protective coating to water to remove the protective coating from the optical devices that are diced.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 31, 2023
    Inventors: Yingdong LUO, Kangkang WANG, Wei-Sheng LEI, Xiaopei DENG, Erica CHEN, Kang LUO, Daihua ZHANG, Rami HOURANI, Ludovic GODET
  • Patent number: 11742330
    Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: August 29, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Kurtis Leschkies, Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Jeffrey L. Franklin, Wei-Sheng Lei
  • Publication number: 20230268418
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventors: Kuo-Cheng CHIANG, Chen-Feng HSU, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung Ying LEE, Wei-sheng YUN, Yu-Lin YANG
  • Publication number: 20230263081
    Abstract: A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Kerem Akarvardar, Yu Chao LIN, Wei-Sheng Yun, Shao-Ming Yu, Tzu-Chiang Chen, Tung Ying Lee
  • Patent number: 11721594
    Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
  • Patent number: 11713097
    Abstract: A harmonic drive system for a pedal-electric-cycle comprises a transmission gear device including a wave generator assembled by an elliptical cam and a flexible bearing, a flexible-flexspline, a rigid-circular-spline having rigid-circular-spline internal gear teeth, a gear set, and a one-way clutch having an inner surface defining a space for containing a spindle of the pedal-electric-cycle. A first end of the flexible-flexspline has flexible-flexspline external gear teeth for meshing with the rigid-circular-spline internal gear teeth and an inner surface defining a space for containing the wave generator. The gear set has a first input portion connected to a second end of the flexible-flexspline, a second input portion having an inner surface defining a space for containing the one-way clutch, and an output portion connected to a sprocket of the pedal-electric-cycle. The first input portion has a first-input rotational axis. The second input portion has a second-input rotational axis.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 1, 2023
    Assignee: ZHUHAI KWUNHING MACHINERY & ELECTRONIC CO. LTD.
    Inventors: Pei Yu Wang, Wei Sheng Ke
  • Publication number: 20230238451
    Abstract: A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Tung-Ying LEE, Chih-Chieh YEH
  • Publication number: 20230231054
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao LIN, Wei-Sheng YUN, Tung-Ying LEE
  • Patent number: 11705909
    Abstract: A frequency-locked circuit for a variable frequency topology is configured to trigger a Pulse Width Modulation (PWM) controller to lock a frequency of a driving signal outputted by the PWM controller. The frequency-locked circuit includes an AC wave generating circuit and a comparator. The AC wave generating circuit receives and converts the driving signal to generate an AC wave signal. The comparator is electrically connected to the AC wave generating circuit and receives the AC wave signal. The comparator compares the AC wave signal with a reference signal to generate a comparison output signal. In response to determining that the AC wave signal is greater than the reference signal, the comparison output signal triggers the PWM controller to convert the driving signal from one voltage level to another voltage level so as to lock the frequency. The one voltage level is different from the another voltage level.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: July 18, 2023
    Assignee: P-DUKE TECHNOLOGY CO., LTD.
    Inventors: Tien-Yu Chen, Liang-Jhou Dai, Wei-Sheng Wang, Hsiao-Hua Chi, Lien-Hsing Chen
  • Patent number: D993422
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 25, 2023
    Assignee: Jiangyu Kangjian Innovation Medical Technology(Chengdu) Co., Ltd
    Inventors: Chieh Kuo, Ying-Wei Sheng, Ping-Hao Liu