Abstract: Exemplary processing methods may include translating a lithium film beneath a first showerhead. The methods may include introducing an oxidizer gas through the first showerhead onto the lithium film. The methods may include forming an oxide monolayer on the lithium film. The oxide monolayer may be or include the oxidizer gas adsorbed on the lithium film. The methods may include translating the lithium film beneath a second showerhead after forming the oxide monolayer. The methods may include introducing a carbon source gas through the first showerhead onto the lithium film. The methods may also include converting the oxide monolayer into a carbonate passivation layer through reaction of the oxide monolayer with the carbon source gas.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, a breakthrough treatment is performed, the breakthrough treatment comprising a first physical bombardment operation, a second iterative isotropic and directional plasma etch operation, and a third directional breakthrough operation. Subsequent to performing the breakthrough treatment, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer.

Abstract: The disclosure discloses a network system, a wireless network extender, and a network provider. The network system includes a network provider, a wireless network router, and a wireless network extender. The wireless network extender includes a communication unit and an extension unit. The wireless network extender connects to the wireless network router through a first communication channel provided by the communication unit and communicates with the network provider through the wireless network router, or communicates with the network provider through a second communication channel provided by the extension unit. When the first communication channel is unavailable, the wireless network extender connects to the network provider through the second communication channel. The first communication channel and the second communication channel use different communication protocols. The disclosure can provide a mesh network with a redundancy mechanism for diagnosis/management using different communication protocols.

Abstract: A method for measuring wafer bow value comprising the following steps is provided. Place a wafer on a wafer chuck apparatus. A gas inlet process is performed on gas inlet passageways of a passageway pair of the wafer chuck apparatus. A gas outlet process is performed on gas outlet passageways of a passageway pair of the wafer chuck apparatus. A leak rate of each channel pair is measured by the control unit when the wafer is placed on the wafer chuck apparatus and during the gas inlet process and gas outlet process are performed. A wafer bow value of the wafer on the wafer chuck apparatus is estimated by the leak rate of the passageway pair. A wafer chuck apparatus is provided. A semiconductor process flow is provided.

Abstract: This invention relates to compounds of the general formula: in which the variable groups are as defined herein, and to their preparation and use.

Abstract: The invention relates to c-Kit inhibitors useful in the treatment of cancers, and other serine-threonine kinase mediated diseases, having the Formula: (I) where A, L, R1, R2, R3, and n are described herein.

Abstract: A touch module includes a substrate, a touch sensing layer, a first transparent adhesive layer, and a second transparent adhesive layer. The substrate has a visible area and a peripheral area surrounding the visible area. The touch sensing layer is disposed on the substrate and located in the visible area. The first transparent adhesive layer is disposed on the touch sensing layer, and a dielectric constant of the first transparent adhesive layer is between 1.5 and 3.0. The second transparent adhesive layer is disposed on the first transparent adhesive layer, and a dielectric constant of the second transparent adhesive layer is between 3.0 and 8.0.

Abstract: Apparatus and methods related to image processing are provided. A computing device can determine a first image area of an image, such as an image captured by a camera. The computing device can determine a warping mesh for the image with a first portion of the warping mesh associated with the first image area. The computing device can determine a cost function for the warping mesh by: determining first costs associated with the first portion of the warping mesh that include costs associated with face-related transformations of the first image area to correct geometric distortions. The computing device can determine an optimized mesh based on optimizing the cost function. The computing device can modify the first image area based on the optimized mesh.

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

Abstract: A method for recovering a resource from a CIGS thin-film solar cell to be recycled includes a) providing the CIGS thin-film solar cell, and b) subjecting the CIGS thin-film solar cell to a cooling treatment at a predetermined temperature, such that a light absorbing unit of the CIGS thin-film solar cell can be recovered due to thermal strain difference of materials of the CIGS thin-film solar cell.

Abstract: In an embodiment, a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer is provided. The method includes detecting the mask layer by a sensor, the mask layer providing a substrate surface; determining a property of the blind via, the property comprising one or more of a top diameter, a bottom diameter, a volume, or a taper angle; focusing a Gaussian laser beam, under laser process parameters, at the substrate surface to remove at least a portion of the mask layer; adjusting the laser process parameters based on the property; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. The mask layer can be pre-etched. Apparatus for forming a blind via in a substrate are also provided.

Abstract: A device is applicable to a display driver, including a sampling circuit and a logic circuit. The sampling circuit is configured to sample a command signal by recording a plurality of command values of the command signal at different times. The plurality of command values corresponds to at least one data line of a pixel circuit. The logic circuit is electrically coupled to the sampling circuit, and is configured to receive the plurality of command values. The logic circuit is further configured to generate a filtered command signal according to the plurality of command values, and is configured to provide the filtered command signal to drive the pixel circuit.

Abstract: A spliced display including a transparent substrate, a plurality of light emitting diode modules, at least one control element and a signal transmission structure is provided. The transparent substrate has a display surface and a back surface opposite to each other. The light emitting diode modules are disposed on the back surface of the transparent substrate to be spliced with each other. Each of the light emitting diode modules includes a driving backplane and a plurality of micro light emitting diodes, and the micro LEDs are disposed in an array between the driving backplane and the transparent substrate. The control element is disposed on the transparent substrate. The control element is connected to the light emitting diode modules via the signal transmission structure, and the light emitting diode modules are connected to each other via the signal transmission structure.

Abstract: The invention relates to c-Kit inhibitors useful in the treatment of cancers, and other serine-threonine kinase mediated diseases, having the Formula: wherein A, L, R1, R2, R3, and n are described herein.

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.

Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.

Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.