Patents by Inventor Wei Su

Wei Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240153949
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • Publication number: 20240150900
    Abstract: An anti-cavitation damping composite metal structure for a flow passage component and a preparation method thereof are provided. The preparation method includes: cladding a gradient functional material layer by layer on a substrate of a flow passage component; forming periodic structures on a surface of each layer of the gradient functional material through etching by an ultrafast laser to absorb a part of an impact load energy caused by cavitation of the flow passage component, where the layers of the gradient functional material form a gradient coating with a toughness increasing layer by layer and a hardness decreasing layer by layer from bottom to top; and forming nano twins on a surface layer by a laser shock peening technique, and implanting a residual compressive stress to further improve anti-cavitation resistance of a surface.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Applicant: HOHAI UNIVERSITY
    Inventors: Hongbing YAO, Yuanhang ZHOU, Wenlong LI, Wenjie SHI, Wei SU, Jiang YUE, Xiang HE, Yuanyuan XIANG, Weihua ZHU
  • Patent number: 11978802
    Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wei Hsu, Chih-Hao Wang, Huan-Chieh Su, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu
  • Publication number: 20240139693
    Abstract: A gas infusion tank for a beverage machine includes a tank body defining a holding space for accommodating beverages. A mixing element includes a mixing chamber, an ascending pipe, and a descending pipe. A top of the ascending pipe is fluidly connected to the mixing chamber and a bottom of the ascending pipe has a liquid inlet. The liquid inlet is fluidly connected to the holding space. A top of the descending pipe is fluidly connected to the mixing chamber and a bottom of the descending pipe includes a liquid outlet in fluid communication with the nozzle. A gas intake hole connects the holding space with the mixing chamber.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 2, 2024
    Applicants: Marmon Foodservice Technologies, Inc., Cornelius (Tianjin) Co., Ltd.
    Inventors: Jacob C. Greenberg, Nicholas M. Giardino, Yulong Liu, Wei Xing, Qi Zheng, Weidong Song, Wenzhai Su, Peiyuan Yang, Tinghao Chen
  • Patent number: 11973254
    Abstract: An electrochemical cell and battery system including cells, each cell including a catholyte, an anolyte, and a separator disposed between the catholyte and anolyte and that is permeable to the at least one ionic species (for example, a metal cation or the hydroxide ion). The catholyte solution includes a ferricyanide, permanganate, manganate, sulfur, and/or polysulfide compound, and the anolyte includes a sulfide and/or polysulfide compound. These electrochemical couples may be embodied in various physical architectures, including static (non-flowing) architectures or in flow battery (flowing) architectures.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 30, 2024
    Assignee: FORM ENERGY, INC.
    Inventors: Liang Su, Wei Xie, Yet-Ming Chiang, William Henry Woodford, Lucas Cohen, Jessa Silver, Katelyn Ripley, Eric Weber, Marco Ferrara, Mateo Cristian Jaramillo, Theodore Alan Wiley
  • Publication number: 20240136203
    Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen
  • Publication number: 20240132502
    Abstract: The present disclosure relates to novel compounds that degrade Bruton's tyrosine kinase (BTK), pharmaceutical compositions containing such compounds, and their use in prevention and treatment of conditions modulated by BTK.
    Type: Application
    Filed: February 2, 2022
    Publication date: April 25, 2024
    Applicant: ACCUTAR BIOTECHNOLOGY INC.
    Inventors: Yimin Qian, Wei HE, Robert LUO, Jie SU, Hui ZHANG, Ke LIU, Jie FAN
  • Publication number: 20240136226
    Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Li-Wei CHU, Ying-Chi SU, Yu-Kai CHEN, Wei-Yip LOH, Hung-Hsu CHEN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240134557
    Abstract: An in-place data recovery method and system include receiving a user request to restore a virtual machine to a version corresponding to a first point in time, identifying a first snapshot of the virtual machine based on the user request, generating a second snapshot of the virtual machine, identifying a second data block in the second snapshot that includes modified data derived from data content of a first data block in the first snapshot, generating reverse incremental backup data including the first data block, and restoring the virtual machine in-place based on the reverse incremental backup data.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Benjamin Travis Meadowcroft, Disheng Su, Li Ding, Roman Konarev, Samir Rishi Chaudhry, Shirong Wu, Tianpei Zhang, Wei Wang
  • Patent number: 11966551
    Abstract: Disclosed are a metal mesh touch screen and a method for manufacturing a metal mesh touch screen. The metal mesh touch screen includes the first functional electrode layer, a first adhesive layer, a second functional electrode layer and a second adhesive layer placed sequentially. The first functional electrode layer includes the first metal mesh wiring extending in a first direction and a metal material for preparing the first metal mesh wiring is a metal foil with a first rough surface and a second rough surface. The second functional electrode layer includes a second metal mesh wiring extending in a second direction and a metal material for preparing the second metal mesh wiring is the metal foil with the first rough surface and the second rough surface.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Optoelectronics Co., Ltd.
    Inventors: Wei Su, Guoliang Zhang, Shourong Hu
  • Patent number: 11967992
    Abstract: A data transmission method in an optical transport network includes: mapping first-type service data to a payload block at a specific location in a plurality of consecutive payload blocks, where the plurality of consecutive payload blocks occupy a payload area of an optical data unit (ODU) frame; mapping second-type service data to a payload block at any location in the plurality of consecutive payload blocks other than the at least one specific location; mapping the ODU frame to an optical transport unit (OTU) frame or a flexible OTN (FlexO) frame; and sending the OTU frame or the FlexO frame. In an applicable scenario, service data is transmitted in a hybrid manner.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: April 23, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wei Su, Qiuyou Wu
  • Patent number: 11966807
    Abstract: A multi-tag concurrent identification method and a system for a query tree based on feature groups are provided in this disclosure. In the disclosure, a whole data string space is divided into a plurality of disjoint subsets according to features of data strings returned by tags, where each of the subsets contains several different data strings, each of the data strings in the each of the subsets is regarded as a complete tag ID or a partial ID, and the each of the subsets corresponds to a unique query prefix, a length of the prefix is fixed and does not dynamically increase with an actual location of a collision, and when multiple data strings from a same subset return at a same time, a reader is capable of identifying them at a same time in a slot.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: April 23, 2024
    Assignee: Nanjing University of Information Science and Technology
    Inventors: Jian Su, Jialin Zhou, Wei Zhuang, Ling Tan
  • Patent number: 11967357
    Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 23, 2024
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Ping-Chun Wu, Li-Yang Hong, Jin-Sheng Ren, Jian-Wei Su
  • Publication number: 20240128232
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
  • Publication number: 20240124437
    Abstract: The present disclosure relates to an injectable lurasidone suspension and a preparation method thereof, and in particular to an irregular form of a lurasidone solid and a pharmaceutical composition thereof. The present disclosure also relates to a preparation method for the solid and the pharmaceutical composition thereof, and an application thereof in the treatment of mental diseases. According to the present disclosure, the lurasidone solid prepared has controllable particle size and has Dv5O particle size of 6 ?m to 110 ?m. The good particle size stability can also he maintained in the pharmaceutical composition. The lurasidone suspension preparation obtained by the method is fast-acting, has a long sustained release period, and can effectively reduce the risk caused by poor patient compliance.
    Type: Application
    Filed: March 21, 2022
    Publication date: April 18, 2024
    Inventors: Ming LI, Xiangyong LIANG, Zhengxing SU, Dan LI, Duo KE, Cong YI, Wei WEI, Guifu DENG, Ya PENG, Dong ZHAO, Jingyi WANG
  • Publication number: 20240125771
    Abstract: The present invention relates to a reaction platform, which comprises: a machine body with a bottom plate for placing non-porous substrates; and a coater module configured on the top of the machine body and capable of maintaining a preset of a predetermined height for moving along the surface of non-porous substrate, wherein the coater module has one or more slits, and a target liquid can be directly injected or sucking in from the outside of the coater module through the slit, and spreading the target liquid onto a surface of the non-porous substrate while moving along the non-porous substrate; wherein the surface of the non-porous substrate has a target to be coated. The reaction platform of the present invention can not only save time, labor and cost, but also have accurate and reproducible experimental results, showing better results than traditional methods.
    Type: Application
    Filed: July 25, 2023
    Publication date: April 18, 2024
    Inventors: An-Bang Wang, Shih-Yu Chen, Tung-Hung Su, Chia-Chi Chu, Chia-Chien Yen, Yu-Wei Chiang
  • Publication number: 20240128218
    Abstract: A semiconductor package includes a first semiconductor substrate, an array of conductive bumps, a second semiconductor substrate, and a spacing pattern. The first semiconductor substrate includes a pad region and an array of first pads disposed within the pad region. The array of conductive bumps is disposed on the array of first pads respectively. The second semiconductor substrate is disposed over the first semiconductor substrate and includes an array of second pads bonded to the array of conductive bumps respectively. The spacing pattern is disposed between the first semiconductor substrate and the second semiconductor substrate, wherein the spacing pattern is located at a periphery of the pad region.
    Type: Application
    Filed: January 19, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Wei-Cheng Wu, Ming-Shih Yeh, An-Jhih Su, Der-Chyang Yeh
  • Patent number: 11960532
    Abstract: An image management method includes: after a video stream sent by a camera is obtained, recognizing a face image in the video stream through face recognition; comparing the image with a face image that is in an area in which the camera is located in a database; and if the comparison fails, expanding the area in which the camera is located around, and then comparing the face image with face images in an area obtained after the area in which the camera is located is expanded.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: April 16, 2024
    Assignee: Huawei Technologies Co., Ltd
    Inventors: Ping Zhang, Wei Su, Ling Deng, Ting Lei