Abstract: A blockchain-based transaction system for a green certificate includes an audit node, a proxy node, and an off-chain node. The proxy node is used by a power producer and a purchaser; the audit node verifies qualification information of the power producer, and send a green certificate to the power producer; the off-chain node predicts a transaction price of a next transaction; when receiving sale information of the power producer and purchase information of the purchaser, the proxy node sends the sale information, a digital signature of the power producer, the purchase information, and a digital signature of the purchaser to the off-chain node; the off-chain node matches the sale information and the purchase information, and sends successfully matched transaction information to the proxy node; the proxy node sends the successfully matched transaction information to a transaction smart contract; and the transaction smart contract performs transaction processing.

Abstract: The present application relates to the technical field of computers. Disclosed are a starting method and apparatus for an Advanced RISC Machine (ARM) server, an ARM server, and a non-volatile computer-readable storage medium. The method includes: after a Basic Input Output System (BIOS) is started, setting a clock frequency of an Inter-Integrated Circuit (I2C) bus to a preset clock frequency by using the BIOS, where the preset clock frequency is a clock frequency at which a baseboard management controller (BMC) reads real-time clock (RTC) time through the I2C bus; initializing the I2C bus by using the BIOS, and starting and entering an operating system; reading the RTC time through the I2C bus by using the BIOS, and determining whether the BIOS successfully reads the RTC time; and if the BIOS successfully reads the RTC time, displaying, under the operating system, system time corresponding to the RTC time.

Abstract: Guided filtering is applied, with a camera raw image as a guidance image, to a first image to generate an intermediate image. A dynamic range mapping is performed on the intermediate image to generate a second image of a different dynamic range. The second image is used to generate specific local reshaping function index values for selecting specific local reshaping functions. The specific local reshaping functions are applied to the second image to generate a locally reshaped image.

Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: A rendering method includes first constructing a first phase field based on information about a to-be-rendered zone, where the first phase field indicates density distribution in the to-be-rendered zone; obtaining acting force on the to-be-rendered zone, where the fluid flows under action of the external force; obtaining, with reference to the first phase field, velocity distribution of each point in the to-be-rendered zone; performing an advection operation on the first phase field based on the velocity field to obtain a second phase field, wherein the second phase field comprises density distribution obtained by performing the advection operation on the fluid in the to-be-rendered zone; and rendering the to-be-rendered zone based on the second phase field to obtain a rendering frame.

Abstract: This disclosure relates to methods and devices for mitigating overheating in a user equipment device (UE). The UE is configured to communicate over each of LTE and 5G NR and may be configured to communicate through 5G NR over each of a Sub-6 GHz and a millimeter Wave (mmW) frequency band. The UE is configured to establish an ENDC connection with an enB and one or more gNBs. The UE implements intelligent transmission modification and cell measurement adjustments to mitigate overheating and reduce battery drain.

Abstract: A heat dissipation device includes a vapor chamber for contacting a heat source; at least one heat pipe having a first end and a second end connected to the vapor chamber; at least one partition disposed inside the heat pipe to partition the inside of the heat pipe into a first channel and a second channel isolated from each other; and a heat dissipation fin set disposed on the vapor chamber and partially covers the heat pipe. The vapor chamber is filled with a liquid working medium that absorbs the heat of the heat source and then gasifies into a gaseous working medium. The gaseous working medium moves into the first channel and the second channel to be condensed by the heat dissipation fin set, so the gaseous working medium is liquefied into the liquid working medium, and then the liquid working medium flows back into the vapor chamber.

Abstract: The present application relates to the technical field of computers. Disclosed are a starting method and apparatus for an Advanced RISC Machine (ARM) server, an ARM server, and a non-volatile computer-readable storage medium. The method includes: after a Basic Input Output System (BIOS) is started, setting a clock frequency of an Inter-Integrated Circuit (I2C) bus to a preset clock frequency by using the BIOS, where the preset clock frequency is a clock frequency at which a baseboard management controller (BMC) reads real-time clock (RTC) time through the I2C bus; initializing the I2C bus by using the BIOS, and starting and entering an operating system; reading the RTC time through the I2C bus by using the BIOS, and determining whether the BIOS successfully reads the RTC time; and if the BIOS successfully reads the RTC time, displaying, under the operating system, system time corresponding to the RTC time.

Abstract: Embodiments of the present invention disclose an optical module, a related apparatus, and an assembly method. in one example, an optical module includes a first circuit board, a second circuit board, and a connection board. The first circuit board includes a transmitter optical subassembly and a receiver optical subassembly. The second circuit board includes a processing unit. The first circuit board further includes a first connection port. The second circuit board further includes a second connection port. The transmitter optical subassembly and the receiver optical subassembly are separately connected to the first connection port. The processing unit is connected to the second connection port.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.

Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Abstract: A method for manufacturing a semiconductor device includes: forming a feature in a dielectric layer disposed on a semiconductor substrate, the dielectric layer including silicon oxide, the feature extending downwardly from a top surface of the dielectric layer and including silicon, a nitride compound, a low-k dielectric material other than silicon oxide, or combinations thereof; and selectively etching the dielectric layer using an etchant composition to form a trench extending downwardly from the top surface of the dielectric layer, the etchant composition including a hydrogen halide and a nitrogen-containing compound represented by Formula (A), wherein R1, R2, R3 are each independently hydrogen, methyl, or ethyl.

Abstract: A data migration method and a related apparatus are provided. An example migration scheduling apparatus determines a migration task of migrating data of a first file from a source device to a destination device, and performs a first change on metadata of the first file, to trigger the source device or the destination device to complete the migration task based on the first change performed on the metadata of the first file.

Abstract: An all-oxide transistor structure includes a substrate, a first transistor, a second transistor, a third transistor and a fourth transistor. The substrate has an upper surface. The first transistor is disposed on the upper surface of the substrate. The second transistor is disposed on the upper surface of the substrate, wherein the second transistor is electrically connected to the first transistor. The third transistor is electrically connected to the second transistor and overlapped with the second transistor in a first direction, wherein the first direction is parallel to a normal direction of the upper surface of the substrate. The fourth transistor is disposed on the upper surface of the substrate, wherein the fourth transistor is electrically connected to the first transistor, the second transistor and the third transistor.

Abstract: The application belongs to the technical field of sex identification of Apostichopus japonicus, and particularly relates to a molecular marker for sex identification of Apostichopus japonicus and use thereof. The molecular marker, C77185, has a nucleotide sequence set forth in SEQ ID NO: 1. The molecular marker for sex identification of Apostichopus japonicus provided by this application may realize accurate sex identification of Apostichopus japonicus from different geographical populations, which is characteristic of practicability, accuracy, high efficiency and the like, and may be used in the actual production process. The molecular marker may be further used for in vivo sex identification in related research of the Apostichopus japonicus, thereby conducting experimental research on a specific sex.

Abstract: A cell site device and an associated clock synchronization method are provided. The cell site device includes a clock synchronizer, a first processing circuit, and a second processing circuit. The clock synchronizer generates a first operation clock and a second operation clock. The first operation clock and the second operation clock have a specific synchronous relationship, and the clock synchronizer is adjusted by a synchronizer setting signal. The first processing circuit generates the synchronizer setting signal according to one of an external clock synchronization source and an internal clock signal. The clock synchronizer respectively transmits the first operation clock and the second operation clock to the first processing circuit and the second processing circuit. The first processing circuit generates a cross-unit periodic synchronization signal and transmits the cross-unit periodic synchronization signal to the second processing circuit.

Abstract: A method is disclosed to dynamically design acceleration units of neural networks. The method comprises steps of generating plural circuit description files through a neural network model; reading a model weight of the neural network model to determine a model data format of the neural network model; selecting one circuit description file from the plural circuit description files according to the model data format, so that the chip is reconfigured according to the selected circuit description file to form an acceleration unit adapted to the model data format. The acceleration unit is suitable for running a data segmentation algorithm, which may accelerate the inference process of the neural network model. Through this method the chip may be dynamically reconfigured into an efficient acceleration unit for the different model data format, thereby speeding up the inference process of the neural network model.

Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.