Patents by Inventor Wei Su

Wei Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063839
    Abstract: A method for dynamically controlling a radio frequency circuit, a modem chip and a communication device are provided. The method for dynamically controlling the radio frequency circuit includes the following steps. At least one operation information is obtained. The operation information includes a software information, a hardware information and a firmware information. A plurality of working modes of the radio frequency circuit are switched to fit the operation information.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 22, 2024
    Inventors: Chun-Wei SU, Wei-Yi WANG, Yuan-Hwui CHUNG, Tz-Yuan SHIU
  • Patent number: 11904482
    Abstract: A mechanical arm calibration system and a mechanical arm calibration method are provided. The method includes: locating a position of an end point of a mechanical arm in a three-dimensional space to calculate an actual motion trajectory of the end point when the mechanical arm is operating; retrieving link parameters of the mechanical arm, randomly generating sets of particles including compensation amounts for the link parameters through particle swarm optimization (PSO), importing the compensation amounts of each of the sets of particles into forward kinematics after addition of the corresponding link parameters, to calculate an adaptive motion trajectory of the end point; calculating position errors between the adaptive motion trajectory and the actual motion trajectory of each of the sets of particles for a fitness value of the PSO to estimate a group best position; and updating the link parameters by the compensation amounts corresponding to the group best position.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: February 20, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Jun-Yi Jiang, Yen-Cheng Chen, Chung-Yin Chang, Guan-Wei Su, Qi-Zheng Yang
  • Patent number: 11910135
    Abstract: An optical signal transmission method includes mapping a first optical data unit frame to a first flexible tributary unit frame, where the first flexible tributary unit frame includes a plurality of payload blocks; mapping the first flexible tributary unit frame to a first optical payload unit frame, where the plurality of payload blocks are distributed in a payload area of the first optical payload unit frame; mapping the first optical payload unit frame to a second optical data unit frame, where a bit rate of the second optical data unit frame is greater than a bit rate of the first optical data unit frame; mapping the second optical data unit frame to a first optical transport unit frame; and sending the first optical transport unit frame.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: February 20, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wei Su, Qiuyou Wu, Junling Xiang
  • Patent number: 11907636
    Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, Kuopei Lu, Lester Chang, Ze-Ming Wu
  • Publication number: 20240056209
    Abstract: A method and an apparatus determines a network device receiving a first signal and at least one second signal, wherein the first signal carries data to be sent through a first flexible Ethernet interface. A first physical layer clock is determined based on the first signal. A second physical layer clock is determined based on the at least one second signal or the first physical layer clock and the at least one second signal. The first physical layer clock or the second physical layer clock is used as a sending clock of a non-flexible Ethernet interface. The network device includes the first flexible Ethernet interface and the non-flexible Ethernet interface.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 15, 2024
    Inventors: Jingfei Lyu, Fanshun Meng, Jinhui Wang, Wei Su
  • Patent number: 11902718
    Abstract: A service data transmission method, a related device, and a digital processing chip, to reduce a transmission latency of service data. The method in the embodiments includes the following steps: a first device encapsulates a channel frame in a transmission frame, where the channel frame is used to carry service data. Next, the first device sends the transmission frame to a second device. A transmission manner of the channel frame is a non-decapsulation manner between an optical transport network and an access network.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 13, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Junling Xiang, Wei Su
  • Publication number: 20240045145
    Abstract: An optical module for bi-directional monochromatic transmission is provided. The optical module includes a substrate, a common terminal, a circulator module, a multiplex-demultiplex (MDM) module, and an input-output terminal. The common terminal is adjacent to the substrate and connected to an optical fiber. The circulator module is on the substrate and in free space optical communication with the common terminal The MDM module is on the substrate and in free space optical communication with the circulator. The input-output terminal is on the substrate and in free space optical communication with the MDM module, the input-output terminal being configured to connect to an emitter and a receiver. The circulator is configured to spatially separate a first directional transmission to the MDM module from a second directional transmission from the MDM module.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Inventors: HSIU-WEI SU, CHANG-YI PENG
  • Patent number: 11892409
    Abstract: The present invention includes a shell, a light emitter, a beam splitter, a convergent lens, an optical filter, a collimation unit, a discrete light detection unit, and a processing unit. The shell includes a sample well to contain a sample. The light emitter generates a detection beam towards the beam splitter, the detection beam is reflected by the beam splitter before being converged by the convergent lens onto the sample, and a Raman scattered beam is scattered from the sample. The Raman scattered beam respectively passes through the convergent lens, the beam splitter, the optical filter, and the collimation unit, allowing the collimation unit to collimate the Raman scattered beam into a collimated beam. The discrete light detection unit generates multiple light intensity signals according to the collimated beam received, and the processing unit generates a detection result according to the light intensity signals to help detect toxins.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: February 6, 2024
    Assignee: Taiwan RedEye Biomedical Inc.
    Inventors: Tsung-Jui Lin, Shuo-Ting Yan, Kuan-Wei Su
  • Publication number: 20240036001
    Abstract: A substrate has a first side and a second side opposite the first side. A first transistor has a first gate, a second transistor has a second gate, and a third transistor has a third gate. The first gate, the second gate, and the third gate are each disposed over the first side of the substrate. The second gate is disposed between the first gate and the third gate. The first gate and the third gate have different material compositions. A structure is disposed over the second side of the substrate. The structure includes a first opening aligned with the first transistor, a second opening aligned with the second transistor, and a third opening aligned with the third transistor. A sensing film is disposed over the second side of the substrate. The sensing film is configured to attach to one or more predefined miniature targets.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Wei Lee, Katherine H. Chiang, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
  • Publication number: 20240036000
    Abstract: A substrate has a first side and a second side vertically opposite to the first side. A sensing transistor is disposed at least in part over the first side of the substrate. A plurality of voltage reference transistors is disposed at least in part over the first side of the substrate. The voltage reference transistors are disposed on different lateral sides of the sensing transistor. A structure is disposed over the second side of the substrate. The structure defines one or more openings configured to collect a fluid. A sensing film is disposed over the second side of the substrate, wherein the sensing transistor is configured to detect, at least in part through capacitive coupling, a presence of one or more predefined miniature targets in the fluid that attach to the sensing film in the opening that is vertically aligned with the sensing transistor.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Wei Lee, Katherine H. Chiang, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
  • Publication number: 20240036598
    Abstract: A key structure includes a baseplate, a keycap and a connecting assembly. The keycap includes a plurality of first pivot portions and a plurality of sliding slots. The connecting assembly includes a first outer frame, two first inner frames, a second outer frame and a second inner frame. The first inner frames are disposed in two accommodating portions of the first outer frame. Two sides of the first outer frame are respectively connected to part of the sliding slots and the baseplate. Two sides of the first inner frame are respectively connected to the first pivot portion and the base plate. Two sides of the second outer frame are respectively connected to part of the sliding slots and the fixing side. Two sides of the second inner frame are respectively pivoted to one of the first inner frames and the base plate.
    Type: Application
    Filed: December 6, 2022
    Publication date: February 1, 2024
    Inventors: SHIN-CHIN WENG, CHIN-PING LIN, SHIH-YU HSU, LIANG-CHUN YEH, BO-WEI SU
  • Publication number: 20240038894
    Abstract: An interconnect structure is disposed over a semiconductor substrate. The interconnect structure includes a plurality of interconnect layers. A first thin-film transistor (TFT) and a second TFT disposed over the semiconductor substrate. The first TFT and the second TFT each vertically extend through at least a subset of the interconnect layers. An opening is formed in the interconnect structure. The opening is disposed between the first TFT and the second TFT. A sensing film is disposed over a bottom surface and side surfaces of the opening.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Wei Lee, Chung-Liang Cheng, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
  • Publication number: 20240029970
    Abstract: A keyboard device includes a substrate, a keycap, a first connection member, and a first elastic arm structure. The substrate has a top surface, and the top surface has an assembling region. The keycap is disposed above the assembling region, and the keycap has a bottom surface facing the assembling region. The first connection member is connected between the keycap and the assembling region, the first connection member includes a first assembly side and a second assembly side opposite to the first assembly side, the first assembly side is pivotally connected to the bottom surface of the keycap, and the second assembly side is pivotally connected to the substrate. The first elastic arm structure includes a connection end and a free end opposite to the connection end, the connection end is connected to the first assembly side, and the free end abuts against the bottom surface of the keycap.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 25, 2024
    Inventors: Shin-Chin Weng, Chih-Ping Lin, Shih-Yu Hsu, Liang-Chun Yeh, Bo-Wei Su
  • Patent number: 11873081
    Abstract: A rotorcraft has a drive system including a main rotor coupled to a main rotor gearbox to rotate the main rotor at a rotor speed, a main engine coupled to the drive system to provide a first power, a supplemental engine coupled, when a first clutch is engaged, to the drive system to provide a second power additive to the first power, and a control system operable to control the main engine and the supplemental engine to provide a total power demand, where the main engine is controlled based on variations in rotor speed and a power compensation command to produce the first power, and the supplemental engine is controlled to produce the second power in response to a supplemental power demand.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: January 16, 2024
    Assignee: Textron Innovations Inc.
    Inventors: Charles Eric Covington, Chia-Wei Su, Darren Gregory Lang, Thomas Parsons, Cody Earl Fegely
  • Patent number: 11862727
    Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: January 2, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Hao Che Feng, Hung Jen Huang, Hsin Min Han, Shih-Wei Su, Ming Shu Chiu, Pi-Hung Chuang, Wei-Hao Huang, Shao-Wei Wang, Ping Wei Huang
  • Publication number: 20230408443
    Abstract: A semiconductor structure includes a sensor, a patterned dielectric layer, and a cover disposed on the patterned dielectric layer. The sensor includes a bio-sensing device and at least one voltage-reference device disposed in proximity to the bio-sensing device. The bio-sensing device includes a first field effect transistor (FET) and a first sensing portion of a sensing film capacitively coupled to the first FET, and the first sensing portion is concave toward the first FET. The at least one voltage-reference device includes a second FET and a second sensing portion of the sensing film capacitively coupled to the second FET. The patterned dielectric layer is disposed on the sensing film and includes at least one sensing well located above the at least one voltage-reference device and the bio-sensing device. The cover includes fluid channels communicating with the at least one sensing wells.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Lee, Katherine H CHIANG, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
  • Publication number: 20230413690
    Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
    Type: Application
    Filed: September 6, 2023
    Publication date: December 21, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Wei Su, Da-Jun Lin, Chih-Wei Chang, Bin-Siang Tsai, Ting-An Chien
  • Publication number: 20230408442
    Abstract: A semiconductor structure includes an isolation structure penetrating through a semiconductor substrate, a biosensor coupled to the semiconductor substrate, and a cover. The biosensor includes a bio-sensing device, a voltage-reference device spaced apart from the bio-sensing device, thermal management devices in proximity to the bio-sensing device, and a patterned dielectric layer. Each of the bio-sensing and voltage-reference devices includes a gate structure disposed on a bottom surface of the semiconductor substrate, S/D regions disposed in the semiconductor substrate, and a portion of a sensing film disposed on the semiconductor substrate and capacitively coupled to the gate structure and the S/D regions. Each thermal management devices includes a gate structure underlying the isolation structure or the semiconductor substrate. The patterned dielectric layer overlying the semiconductor substrate includes sensing wells located above the voltage-reference and bio-sensing devices.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Lee, Katherine H CHIANG, Pei-Wen Liu, Ke-Wei Su, Kuan-Lun Cheng
  • Patent number: 11846877
    Abstract: A method includes: after a panorama shooting instruction triggered by a user is acquired, shooting a first image, and acquiring a shooting parameter of the first image; determining move guiding information according to a preset move guiding policy, and displaying the move guiding information on a terminal, so as to instruct the user to move the terminal according to the move guiding information; shooting a preset quantity of images according to the shooting parameter of the first image after it is detected that the terminal moves, where the preset quantity of images are background images on both the left and right sides of a background corresponding to the first image; and performing, by using the first image as a center and by using a preset splicing scheme, seamless splicing on the first image and the preset quantity of images, to obtain a panoramic image.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: December 19, 2023
    Assignee: Huawei Device Co., Ltd.
    Inventors: Cheng Du, Wei Su, Wei Luo, Bin Deng, Landi Li
  • Publication number: 20230402426
    Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 14, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shih-Hsorng Shen, Chih-Wei Su, Yu-Chun Huo