Abstract: A controlling method for semiconductor process auxiliary apparatus, a control assembly and a manufacturing system are provided. The controlling method includes the following steps. At least one manufacturing parameter of a semiconductor manufacturing processing apparatus are obtained. An energy adjusting signal is generated according to the manufacturing parameter. An auxiliary apparatus controlling signal is generated according to the energy adjusting signal. The semiconductor process auxiliary apparatus is controlled according to the semiconductor auxiliary apparatus controlling signal.

Abstract: Methods, systems, and devices for top die back-side marking for memory systems are described. One or more alignment marks may be added to the back-side of a top memory die in a multi-layer memory device and used to align a position of the top memory die relative to a position of a memory die below the top memory die. The alignment marks may be formed on the top memory die during the manufacturing process of the multi-layer memory device. Operations for forming the alignment marks are described using various semiconductor fabrication techniques. Operations are also disclosed for using the alignment marks to modify placement of the top memory die to reduce the alignment offset in the manufacturing process of subsequent memory dies.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a reader. The reader broadcasts a radio signal indicating an available slot set. The reader transmits an acknowledge (ACK) signal including a decoded sequence to an ambient internet of things (A-IoT) device. The reader receives an identifier from the A-IoT device. The identifier is a reply of the A-IoT device when there is a match between the decoded sequence and a chosen sequence, and the chosen sequence is a random sequence that responds to the radio signal in a random slot chosen from the available slot set.

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Abstract: A thin film transistor includes a stack of an active layer, a gate dielectric, and a gate electrode in a forward order or in a reverse order. The active layer includes a compound semiconductor material containing oxygen, at least one acceptor-type element selected from Ga and W, and at least one heavy post-transition metal element selected from In and Sn. An atomic percentage of the at least one heavy post-transition metal element at a first surface portion of the active layer that contacts the gate dielectric is higher than an atomic percentage of the at least one heavy post-transition metal element at a second surface portion of the active layer located on an opposite side of the gate dielectric. The front channel current may be increased, and the back channel leakage current may be decreased.

Abstract: A projection system, a projection device, and a control method thereof are provided. The control method of the projection device includes the following steps: transmitting a first original command by a terminal device; projecting an adjustment image by the projection device in response to the first original command corresponding to an image correction operation of the projection device, wherein the adjustment image includes at least one pattern array and at least one adjustment reference point; transmitting a second original command by the terminal device; and adjusting a position of the at least one adjustment reference point of the adjustment image by the projection device in response to the second original command corresponding to adjusting the position of the at least one adjustment reference point of the adjustment image, wherein the at least one adjustment reference point is located in the corresponding at least one pattern array.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a reader. The reader receives a response signal set that responds to a radio signal, from an ambient internet of things (A-IoT) device set, a response signal in the response signal set being modulated by a corresponding A-IoT device in the A-IoT device set to include an identification of the corresponding A-IoT device. The reader identifies the corresponding A-IoT device based on the identification of the corresponding A-IoT device, and performs measurement for a positioning parameter. The reader executes a positioning related operation based on the identified A-IoT device and the measurement for the positioning parameter.

Abstract: A semiconductor device includes a semiconductor channel region, a source/drain region, and a contact structure. The semiconductor channel region is over a substrate. The source/drain region is adjacent the semiconductor channel region. The source/drain region has a notched corner. The contact structure has a portion inlaid in the notched corner in the source/drain region.

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

Abstract: A method of forming a semiconductor device includes: forming a device layer that includes nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer, which includes: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer between the first and the second conductive features; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

Abstract: A keycap lifting mechanism increases the stability of supporting a keycap through structure designs of supports. For example, vertical projections of a sliding hole, a holder hole, and a base hole of supports overlap in a short side direction. For another example, vertical projections of a sliding hole, a holder hole, and a pivot hole of supports overlap in the short side direction. For another example, within the coverage range of a dome hole formed by supports in a long side direction, the supports do not have a structure connecting with other components. For another example, within the coverage range of two arms on opposite sides of the dome hole, there are more than 8 connection portions on the supports for connecting with a keycap and a base plate. For another example, the width of the arm is 0.8 to 2 times the length of the arm.

Abstract: A keycap support mechanism increases the stability of supporting a keycap through structure designs of supports. Two supports are pivotally connected around a pivot axis; therein, at least one of the supports includes a support body and a reinforcement part embedded into the support body. The elastic modulus of the reinforcement part is greater than the elastic modulus of the support body. In an embodiment, the reinforcement part has a surrounding portion. The surrounding portion surrounds three sides of a pivot hole of the support. In another embodiment, the two supports both have a reinforcement part. The two reinforcement parts have overlapping portions in a vertical direction. A keyswitch structure includes a base plate, a keycap, and any of the above keycap support mechanisms. The keycap support mechanism supports the keycap above the base plate.

Abstract: A keycap lifting mechanism increases the stability of supporting a keycap through structure designs of supports. For example, a pivot of two supports overlaps base holes of the supports along the pivot axis. For another example, each of supports has support arms extending non-parallel to the pivot axis. The free end of each support arm is connected to a base plate. For another example, among a plurality of pivotally-connecting structures between supports, at least one includes a fully-open pivot hole, achieved by two opposite hooks, and at least one includes a semi-open pivot hole, achieved by two opposite hooks and a blind hole. A long rectangular keyswitch structure includes a keycap and any of the above mechanisms. The distance from a sliding hole of one support to an adjacent keycap long side is greater than the distance from a holder hole of another support to another adjacent keycap long side.

Abstract: A keycap support mechanism increases the stability of supporting a keycap through structure designs of supports. Two supports are pivotally connected around a pivot axis. One of the supports includes a support body and a reinforcement part embedded into the support body. The elastic modulus of the reinforcement part is greater than the elastic modulus of the support body. In an embodiment, the reinforced support includes Z-shaped bending structure extending parallel to the pivotal axis. In another embodiment, the reinforced support has a sliding shaft and a sliding hole formed beside the sliding shaft. The reinforced support is slidably and rotatably connected to the keycap through the sliding shaft. The reinforcement part surrounds the sliding hole and goes through the sliding shaft. A keyswitch structure includes a base plate, a keycap, and any of the above keycap support mechanisms. The keycap support mechanism supports the keycap above the base plate.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.